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Difference between revisions of "intel/core i5/i5-6267u"
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{{intel title|Core i5-6267U}} | {{intel title|Core i5-6267U}} | ||
− | {{ | + | {{chip |
|name=Core i5-6267U | |name=Core i5-6267U | ||
− | |image=skylake ( | + | |image=skylake u (front; iris).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=i5-6267U | |model number=i5-6267U | ||
+ | |part number=FJ8066202499002 | ||
|s-spec=SR2JK | |s-spec=SR2JK | ||
|market=Mobile | |market=Mobile | ||
+ | |first announced=September 1, 2015 | ||
+ | |first launched=September 27, 2015 | ||
+ | |release price=$304.00 | ||
|family=Core i5 | |family=Core i5 | ||
|series=i5-6000 | |series=i5-6000 | ||
Line 13: | Line 17: | ||
|frequency=2,900 MHz | |frequency=2,900 MHz | ||
|turbo frequency1=3,300 MHz | |turbo frequency1=3,300 MHz | ||
+ | |turbo frequency2=3,100 MHz | ||
|bus type=OPI | |bus type=OPI | ||
|bus rate=4 GT/s | |bus rate=4 GT/s | ||
Line 26: | Line 31: | ||
|technology=CMOS | |technology=CMOS | ||
|mcp=Yes | |mcp=Yes | ||
− | |die count= | + | |die count=3 |
|word size=64 bit | |word size=64 bit | ||
|core count=2 | |core count=2 | ||
Line 42: | Line 47: | ||
|package module 1={{packages/intel/fcbga-1356}} | |package module 1={{packages/intel/fcbga-1356}} | ||
}} | }} | ||
− | '''Core i5-6267U''' is a {{arch|64}} [[dual-core]] mid-range performance [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 2.9 GHz with a {{intel|turbo boost}} of up to 3.3 GHz. The i5-6267U has a TDP of 28 W with a configurable-down | + | '''Core i5-6267U''' is a {{arch|64}} [[dual-core]] mid-range performance [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 2.9 GHz with a {{intel|turbo boost}} of up to 3.3 GHz. The i5-6267U has a TDP of 28 W with a configurable TDP-down of 23 W. This chip incorporates the {{intel|Iris Graphics 550}} GPU operating at 300 MHz with a burst frequency of 1.05 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6267U comes with an additional 64 MiB of [[embedded DRAM]] side cache. |
== Cache == | == Cache == | ||
Line 62: | Line 67: | ||
|l3 break=2x2 MiB | |l3 break=2x2 MiB | ||
|l3 policy=write-back | |l3 policy=write-back | ||
+ | |l4 cache=64 MiB | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2133 | ||
+ | |type 2=LPDDR3-1866 | ||
+ | |type 3=DDR3L-1600 | ||
+ | |ecc=No | ||
+ | |max mem=32 GiB | ||
+ | |controllers=1 | ||
+ | |channels=2 | ||
+ | |max bandwidth=31.79 GiB/s | ||
+ | |bandwidth schan=15.89 GiB/s | ||
+ | |bandwidth dchan=31.79 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 12 | ||
+ | | pcie config = 1x4 | ||
+ | | pcie config 2 = 2x2 | ||
+ | | pcie config 3 = 1x2+2x1 | ||
+ | | pcie config 4 = 4x1 | ||
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | The Iris Graphics 550 includes 64 MiB of side eDRAM cache in addition to everything else. | ||
+ | {{integrated graphics | ||
+ | | gpu = Iris Graphics 550 | ||
+ | | device id = 0x1927 | ||
+ | | designer = Intel | ||
+ | | execution units = 48 | ||
+ | | max displays = 3 | ||
+ | | max memory = 32 GiB | ||
+ | | frequency = 300 MHz | ||
+ | | max frequency = 1,050 MHz | ||
+ | |||
+ | | output crt = | ||
+ | | output sdvo = | ||
+ | | output dsi = | ||
+ | | output edp = Yes | ||
+ | | output dp = Yes | ||
+ | | output hdmi = Yes | ||
+ | | output vga = | ||
+ | | output dvi = Yes | ||
+ | |||
+ | | directx ver = 12 | ||
+ | | opengl ver = 4.4 | ||
+ | | opencl ver = 2.0 | ||
+ | | hdmi ver = 1.4a | ||
+ | | dp ver = 1.2 | ||
+ | | edp ver = 1.3 | ||
+ | | max res hdmi = 4096x2304 | ||
+ | | max res hdmi freq = 24 Hz | ||
+ | | max res dp = 4096x2304 | ||
+ | | max res dp freq = 60 Hz | ||
+ | | max res edp = 4096x2304 | ||
+ | | max res edp freq = 60 Hz | ||
+ | | max res vga = | ||
+ | | max res vga freq = | ||
+ | |||
+ | | features = Yes | ||
+ | | intel quick sync = Yes | ||
+ | | intel intru 3d = Yes | ||
+ | | intel insider = | ||
+ | | intel widi = | ||
+ | | intel fdi = | ||
+ | | intel clear video = Yes | ||
+ | | intel clear video hd = Yes | ||
+ | }} | ||
+ | {{skylake hardware accelerated video table|col=1}} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=No | ||
+ | |flex=Yes | ||
+ | |fastmem=No | ||
+ | |isrt=Yes | ||
+ | |sba=No | ||
+ | |mwt=Yes | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=Yes | ||
+ | |tsx=No | ||
+ | |txt=No | ||
+ | |ht=Yes | ||
+ | |vpro=No | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=Yes | ||
+ | |sgx=Yes | ||
+ | |securekey=Yes | ||
+ | |osguard=Yes | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
}} | }} |
Latest revision as of 15:20, 13 December 2017
Edit Values | |||||||||||||
Core i5-6267U | |||||||||||||
General Info | |||||||||||||
Designer | Intel | ||||||||||||
Manufacturer | Intel | ||||||||||||
Model Number | i5-6267U | ||||||||||||
Part Number | FJ8066202499002 | ||||||||||||
S-Spec | SR2JK | ||||||||||||
Market | Mobile | ||||||||||||
Introduction | September 1, 2015 (announced) September 27, 2015 (launched) | ||||||||||||
Release Price | $304.00 | ||||||||||||
Shop | Amazon | ||||||||||||
General Specs | |||||||||||||
Family | Core i5 | ||||||||||||
Series | i5-6000 | ||||||||||||
Locked | Yes | ||||||||||||
Frequency | 2,900 MHz | ||||||||||||
Turbo Frequency | 3,300 MHz (1 core), 3,100 MHz (2 cores) | ||||||||||||
Bus type | OPI | ||||||||||||
Bus rate | 4 GT/s | ||||||||||||
Clock multiplier | 29 | ||||||||||||
Microarchitecture | |||||||||||||
ISA | x86-64 (x86) | ||||||||||||
Microarchitecture | Skylake | ||||||||||||
Core Name | Skylake U | ||||||||||||
Core Family | 6 | ||||||||||||
Core Model | 78 | ||||||||||||
Core Stepping | K1 | ||||||||||||
Process | 14 nm | ||||||||||||
Technology | CMOS | ||||||||||||
MCP | Yes (3 dies) | ||||||||||||
Word Size | 64 bit | ||||||||||||
Cores | 2 | ||||||||||||
Threads | 4 | ||||||||||||
Max Memory | 32 GiB | ||||||||||||
Multiprocessing | |||||||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||||||
Electrical | |||||||||||||
Vcore | 0.55 V-1.52 V | ||||||||||||
TDP | 28 W | ||||||||||||
cTDP down | 23 W | ||||||||||||
Tjunction | 0 °C – 100 °C | ||||||||||||
Tstorage | -25 °C – 125 °C | ||||||||||||
Packaging | |||||||||||||
|
Core i5-6267U is a 64-bit dual-core mid-range performance x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2.9 GHz with a turbo boost of up to 3.3 GHz. The i5-6267U has a TDP of 28 W with a configurable TDP-down of 23 W. This chip incorporates the Iris Graphics 550 GPU operating at 300 MHz with a burst frequency of 1.05 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6267U comes with an additional 64 MiB of embedded DRAM side cache.
Cache[edit]
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Graphics[edit]
The Iris Graphics 550 includes 64 MiB of side eDRAM cache in addition to everything else.
Integrated Graphics Information
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[Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
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Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
VP9 | ✘ | 0 | Unified | 2160p (4K) |
Features[edit]
[Edit/Modify Supported Features]
Facts about "Core i5-6267U - Intel"
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |