Semiconductor & Computer Engineering
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Difference between revisions of "intrinsity/fastmath/fastmath-lp"
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| name = FastMATH-LP | | name = FastMATH-LP | ||
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Latest revision as of 15:31, 13 December 2017
| Edit Values | |
| FastMATH-LP | |
 | |
| General Info | |
| Designer | Intrinsity |
| Manufacturer | TSMC |
| Model Number | FastMATH-LP |
| Market | Embedded |
| Introduction | 2002 (announced) 2003 (launched) |
| General Specs | |
| Family | FastMATH |
| Frequency | 1,000 MHz |
| Bus type | RapidIO |
| Bus speed | 500 MHz |
| Bus rate | 4 GT/s |
| Microarchitecture | |
| Microarchitecture | FashMATH |
| Process | 130 nm |
| Technology | Dynamic CMOS |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 1 GiB |
| Electrical | |
| Power dissipation | 6 W |
| Vcore | 0.85 V |
The FastMATH-LP was a microprocessor developed by Intrinsity operating at 1 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed.
Contents
Cache[edit]
- Main article: FastMATH § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 256 blocks × 16 words/block |
| L1D$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 256 blocks × 16 words/block write-through or write-back mode |
| L2$ | 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB |
1x1 MiB 4-way set associative (configurable as SRAM in 256 KiB increments) |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Memory controller[edit]
| Integrated Memory Controller | |
| Type | DDR-400 |
| Controllers | 1 |
| Channels | 2 |
| Max memory | 1 GB |
Matrix and Vector Unit[edit]
- SIMD architecture
- Operates on 4x4 array of 32-bit elements
- Fixed-point matrix, vector, and scalar data types
Features[edit]
- JTAG interface
- 8-bit or 32-bit wide bus operates up to 66 MHz
Documents[edit]
Manuals[edit]
Facts about "FastMATH-LP - Intrinsity"
| base frequency | 1,000 MHz (1 GHz, 1,000,000 kHz) + |
| bus rate | 4,000 MT/s (4 GT/s, 4,000,000 kT/s) + |
| bus speed | 500 MHz (0.5 GHz, 500,000 kHz) + |
| bus type | RapidIO + |
| core count | 1 + |
| core voltage | 0.85 V (8.5 dV, 85 cV, 850 mV) + |
| designer | Intrinsity + |
| family | FastMATH + |
| first announced | 2002 + |
| first launched | 2003 + |
| full page name | intrinsity/fastmath/fastmath-lp + |
| has feature | JTAG + |
| instance of | microprocessor + |
| l1d$ description | 256 blocks × 16 words/block + |
| l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l1i$ description | 256 blocks × 16 words/block + |
| l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| ldate | 2003 + |
| main image |  + |
| manufacturer | TSMC + |
| market segment | Embedded + |
| max memory | 1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) + |
| microarchitecture | FashMATH + |
| model number | FastMATH-LP + |
| name | FastMATH-LP + |
| power dissipation | 6 W (6,000 mW, 0.00805 hp, 0.006 kW) + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
| technology | Dynamic CMOS + |
| thread count | 1 + |
| word size | 32 bit (4 octets, 8 nibbles) + |
