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Latest revision as of 15:28, 13 December 2017

Edit Values
Xeon E7-4807
General Info
DesignerIntel
ManufacturerIntel
Model NumberE7-4807
Part NumberAT80615006432AB
S-SpecSLC3L
MarketServer
IntroductionApril 5, 2011 (announced)
April 5, 2011 (launched)
End-of-lifeAugust 21, 2015 (last order)
February 5, 2016 (last shipment)
Release Price$890.00
ShopAmazon
General Specs
FamilyXeon E7
SeriesE7-4800
LockedYes
Frequency1,866.66 MHz
Bus typeQPI
Bus rate4.80 GT/s
Clock multiplier14
CPUID206F2
Microarchitecture
MicroarchitectureWestmere
PlatformBoxboro
ChipsetBoxboro
Core NameWestmere EX
Core Family6
Core Model47
Core SteppingA2
Process32 nm
Transistors2,600,000,000
TechnologyCMOS
Die513 mm²
Word Size64 bit
Cores6
Threads12
Max Memory2 TiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
Electrical
Vcore1.35 V
TDP95 W
Tcase5 °C – 70 °C
Tstorage-40 °C – 85 °C
Packaging
PackageFCLGA-8 (LGA)FCLGA-8.svg
Dimension49.1 mm x 56.4 mm x 4.2 mm
Pitch1 mm
Pin Count1567
SocketLGA-1567

Xeon E7-4807 is a 64-bit hexa-core x86 data center microprocessor that supports up to 4 sockets. This first generation (Westmere-based) Xeon E7 processor operates at 1.86 GHz with 95 W TDP but does not support turbo boost technology. This processor supports up to 4 channels of DDR3, supporting up to 2 TB of memory.

Cache[edit]

Main article: Westmere § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
393,216 B
0.375 MiB
L1I$192 KiB
196,608 B
0.188 MiB
6x32 KiB4-way set associativewrite-back
L1D$192 KiB
196,608 B
0.188 MiB
6x32 KiB8-way set associativewrite-back
L2$1.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
  6x256 KiB8-way set associativewrite-back
L3$18 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
  6x3 MiB16-way set associativewrite-back

Graphics[edit]

This SoC has no integrated graphics processing unit.

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-800
Supports ECCYes
Max Mem2 TiB
Controllers1
Channels4
Max Bandwidth23.84 GiB/s
24,412.16 MiB/s
25.598 GB/s
25,598.005 MB/s
0.0233 TiB/s
0.0256 TB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s
Triple 17.88 GiB/s
Quad 23.84 GiB/s

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AESAES Encryption Instructions
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
EISTEnhanced SpeedStep Technology
TXTTrusted Execution Technology (SMX)
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e7/e7-4807&oldid=71031"
Facts about "Xeon E7-4807 - Intel"
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has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d + and Extended Page Tables +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size384 KiB (393,216 B, 0.375 MiB) +
l1d$ description8-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description4-way set associative +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ description8-way set associative +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l3$ description16-way set associative +
l3$ size18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) +
max memory bandwidth23.84 GiB/s (24,412.16 MiB/s, 25.598 GB/s, 25,598.005 MB/s, 0.0233 TiB/s, 0.0256 TB/s) +
max memory channels4 +
supported memory typeDDR3-800 +