From WikiChip
Difference between revisions of "intel/xeon e5/e5-2650l v4"
< intel‎ | xeon e5

m (Bot: corrected param)
m (Bot: moving all {{mpu}} to {{chip}})
 
(2 intermediate revisions by the same user not shown)
Line 1: Line 1:
 
{{intel title|Xeon E5-2650L v4}}
 
{{intel title|Xeon E5-2650L v4}}
−
{{mpu
+
{{chip
 
| name                = Xeon E5-2650L v4
 
| name                = Xeon E5-2650L v4
 
| no image            = Yes
 
| no image            = Yes
Line 135: Line 135:
  
 
== Expansions ==
 
== Expansions ==
−
{{mpu expansions
+
{{expansions
 
| pcie revision      = 3.0
 
| pcie revision      = 3.0
 
| pcie lanes        = 40
 
| pcie lanes        = 40
Line 144: Line 144:
  
 
== Features ==  
 
== Features ==  
−
{{mpu features
+
{{x86 features
 
| em64t      = Yes
 
| em64t      = Yes
 
| nx          = Yes
 
| nx          = Yes

Latest revision as of 15:27, 13 December 2017

Edit Values
Xeon E5-2650L v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-2650L v4
Part NumberCM8066002033006
S-SpecSR2N8
QK93 (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
Release Price$1329.00
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-2000
LockedYes
Frequency1,700 MHz
Turbo FrequencyYes
Turbo Frequency2,500 MHz (1 core),
2,500 MHz (2 cores),
2,300 MHz (3 cores),
2,200 MHz (4 cores),
2,100 MHz (5 cores),
2,000 MHz (6 cores),
2,000 MHz (7 cores),
2,000 MHz (8 cores),
2,000 MHz (9 cores),
2,000 MHz (10 cores),
2,000 MHz (11 cores),
2,000 MHz (12 cores),
2,000 MHz (13 cores),
2,000 MHz (14 cores)
Bus typeQPI
Bus speed4,800 MHz
Bus rate2 × 9.6 GT/s
Clock multiplier17
CPUID406F1
Microarchitecture
MicroarchitectureBroadwell
PlatformGrantley EP 2S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingM0
Process14 nm
Transistors4,700,000,000
TechnologyCMOS
Die306.18 mm²
Word Size64 bit
Cores14
Threads28
Max Memory1,536 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP65 W
Tcase0 °C – 64 °C
Tstorage-25 °C – 125 °C

The Xeon E5-2650L v4 is a 64-bit tetradeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for low-power 2S environments. Operating at 1.7 GHz with a turbo boost frequency of 2.5 GHz for a single active core, this MPU has a TDP of 65 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 448 KiB
458,752 B
0.438 MiB
14x32 KiB 8-way set associative (per core, write-back)
L1D$ 448 KiB
458,752 B
0.438 MiB
14x32 KiB 8-way set associative (per core, write-back)
L2$ 3.5 MiB
3,584 KiB
3,670,016 B
0.00342 GiB
14x256 KiB 8-way set associative (per core, write-back)
L3$ 35 MiB
35,840 KiB
36,700,160 B
0.0342 GiB
14x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2650l_v4&oldid=70992"
Facts about "Xeon E5-2650L v4 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size448 KiB (458,752 B, 0.438 MiB) +
l1i$ description8-way set associative +
l1i$ size448 KiB (458,752 B, 0.438 MiB) +
l2$ description8-way set associative +
l2$ size3.5 MiB (3,584 KiB, 3,670,016 B, 0.00342 GiB) +
l3$ description20-way set associative +
l3$ size35 MiB (35,840 KiB, 36,700,160 B, 0.0342 GiB) +