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Latest revision as of 15:12, 13 December 2017

Edit Values
Cavium CN5745-1000 SSP
Octeon CN57xx.svg
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN5745-1000 SSP
Part NumberCN5745-1000BG1217-SSP
MarketStorage
IntroductionJun 26, 2007 (announced)
August, 2007 (launched)
General Specs
FamilyOCTEON Plus
SeriesCN57xx
Frequency1,000 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Process90 nm
TechnologyCMOS
Word Size64 bit
Cores10
Threads10
Multiprocessing
Max SMP1-Way (Uniprocessor)
Packaging
PackageFCBGA-1217 (BGA)
Dimension40 mm x 40 mm
Ball Count1217
InterconnectBGA-1217

CN5745-1000 SSP is a 64-bit deca-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates ten cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$480 KiB
491,520 B
0.469 MiB
L1I$320 KiB
327,680 B
0.313 MiB
10x32 KiB  
L1D$160 KiB
163,840 B
0.156 MiB
10x16 KiB  

L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Controllers1
Channels2
Width64 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision1.0
Max Lanes8
Configsx4, x8
UART

GP I/OYes


Networking[edit]

Interface options:

  • 8-lanes PCIe + 8-lanes PCIe
  • 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
  • 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
XAUIYes (Ports: 1)
SGMIIYes (Ports: 4)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Encryption
Hardware ImplementationYes
Types3DES, AES-GCM, AES up to 256-bit, SHA-1, SHA-2 up to SHA-512, RSA up to 8192, DH
Networking
TCPYes
QoSYes
Compression
CompressionYes
DecompressionYes
RAID
RAID 5Yes
RAID 6Yes

Block diagram[edit]

cn57xx block diagram.png

Datasheet[edit]

Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN5745-1000 SSP - Cavium#io +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
l1$ size480 KiB (491,520 B, 0.469 MiB) +
l1d$ size160 KiB (163,840 B, 0.156 MiB) +
l1i$ size320 KiB (327,680 B, 0.313 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
max pcie lanes8 +
supported memory typeDDR2-800 +