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Difference between revisions of "cavium/octeon/cn3830-400bg1521-nsp"
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| name = Cavium CN3830-400 NSP | | name = Cavium CN3830-400 NSP | ||
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Latest revision as of 16:11, 13 December 2017
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Cavium CN3830-400 NSP | |||||||
General Info | |||||||
Designer | Cavium | ||||||
Manufacturer | TSMC | ||||||
Model Number | CN3830-400 NSP | ||||||
Part Number | CN3830-400BG1521-NSP | ||||||
Market | Networking | ||||||
Introduction | September 13, 2004 (announced) June 1, 2005 (launched) | ||||||
General Specs | |||||||
Family | OCTEON | ||||||
Series | CN3800 | ||||||
Frequency | 400 MHz | ||||||
Microarchitecture | |||||||
ISA | MIPS64 (MIPS) | ||||||
Microarchitecture | cnMIPS | ||||||
Core Name | cnMIPS | ||||||
Process | 130 nm | ||||||
Technology | CMOS | ||||||
Word Size | 64 bit | ||||||
Cores | 4 | ||||||
Threads | 4 | ||||||
Max Memory | 16 GiB | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Packaging | |||||||
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The CN3830-400 NSP is a 64-bit quad-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2005. This processor, which incorporates four cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Networking[edit]
Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN3830-400 NSP - Cavium"
has ecc memory support | true + |
has hardware accelerators for cryptography | true + |
has hardware accelerators for data compression | true + |
has hardware accelerators for data decompression | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for regular expression | true + |
has hardware accelerators for tcp packet processing | true + |
l1$ size | 160 KiB (163,840 B, 0.156 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 64-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR2-800 + |