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Difference between revisions of "intrinsity/fastmath/fastmath-2"
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{{intrinsity title|FastMATH 2 GHz}}
 
{{intrinsity title|FastMATH 2 GHz}}
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| name                = FastMATH 2 GHz
 
| name                = FastMATH 2 GHz
 
| no image            = Yes
 
| no image            = Yes
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| model number        = FastMATH-2
 
| model number        = FastMATH-2
 
| part number        =  
 
| part number        =  
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| part number 1       =  
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| part number 2       =  
 
| market              = Embedded
 
| market              = Embedded
 
| first announced    = 2001
 
| first announced    = 2001

Latest revision as of 15:30, 13 December 2017

Edit Values
FastMATH 2 GHz
General Info
DesignerIntrinsity
ManufacturerTSMC
Model NumberFastMATH-2
MarketEmbedded
Introduction2001 (announced)
2002 (launched)
General Specs
FamilyFastMATH
Frequency2,000 MHz
Bus typeRapidIO
Bus speed500 MHz
Bus rate4 GT/s
Microarchitecture
MicroarchitectureFashMATH
Process130 nm
TechnologyDynamic CMOS
Word Size32 bit
Cores1
Threads1
Max Memory1 GiB
Electrical
Power dissipation15 W
Vcore1 V

The FastMATH 2 GHz was the flagship microprocessor developed by Intrinsity operating at 2 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit.

Cache[edit]

Main article: FastMATH § Cache
Cache Info [Edit Values]
L1I$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 256 blocks × 16 words/block
L1D$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 256 blocks × 16 words/block write-through or write-back mode
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
1x1 MiB 4-way set associative (configurable as SRAM in 256 KiB increments)

Graphics[edit]

This SoC has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR-400
Controllers 1
Channels 2
Max memory 1 GB

Matrix and Vector Unit[edit]

  • SIMD architecture
  • Operates on 4x4 array of 32-bit elements
  • Fixed-point matrix, vector, and scalar data types

Features[edit]

  • JTAG interface
  • 8-bit or 32-bit wide bus operates up to 66 MHz

Documents[edit]

Manuals[edit]


Retrieved from "https://en.wikichip.org/w/index.php?title=intrinsity/fastmath/fastmath-2&oldid=71119"
Facts about "FastMATH 2 GHz - Intrinsity"
RDF feed
base frequency2,000 MHz (2 GHz, 2,000,000 kHz) +
bus rate4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus speed500 MHz (0.5 GHz, 500,000 kHz) +
bus typeRapidIO +
core count1 +
core voltage1 V (10 dV, 100 cV, 1,000 mV) +
designerIntrinsity +
familyFastMATH +
first announced2001 +
first launched2002 +
full page nameintrinsity/fastmath/fastmath-2 +
has featureJTAG +
instance ofmicroprocessor +
l1d$ description256 blocks × 16 words/block +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description256 blocks × 16 words/block +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate2002 +
manufacturerTSMC +
market segmentEmbedded +
max memory1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
microarchitectureFashMATH +
model numberFastMATH-2 +
nameFastMATH 2 GHz +
power dissipation15 W (15,000 mW, 0.0201 hp, 0.015 kW) +
process130 nm (0.13 μm, 1.3e-4 mm) +
technologyDynamic CMOS +
thread count1 +
word size32 bit (4 octets, 8 nibbles) +