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Difference between revisions of "amd/duron/dhm0850avs1b"
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{{amd title|Duron 850 (Camaro)}} | {{amd title|Duron 850 (Camaro)}} | ||
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| name = Duron 850 | | name = Duron 850 | ||
| no image = Yes | | no image = Yes | ||
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| model number = Duron 850 | | model number = Duron 850 | ||
| part number = DHM0850AVS1B | | part number = DHM0850AVS1B | ||
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| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Mobile | | market = Mobile | ||
| first announced = May 14, 2001 | | first announced = May 14, 2001 | ||
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== Features == | == Features == | ||
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| em64t = | | em64t = | ||
| nx = | | nx = |
Latest revision as of 16:07, 13 December 2017
Edit Values | |
Duron 850 | |
General Info | |
Designer | AMD |
Manufacturer | AMD |
Model Number | Duron 850 |
Part Number | DHM0850AVS1B |
Market | Mobile |
Introduction | May 14, 2001 (announced) May 14, 2001 (launched) |
Shop | Amazon |
General Specs | |
Family | Duron |
Series | Duron Mobile |
Locked | Yes |
Frequency | 850 MHz |
Bus type | FSB |
Bus speed | 100 MHz |
Bus rate | 200 MT/s |
Clock multiplier | 8.5 |
CPUID | 670 |
Microarchitecture | |
Microarchitecture | K7 |
Core Name | Morgan |
Core Family | 6 |
Core Model | 7 |
Core Stepping | 0 |
Process | 180 nm |
Transistors | 25,180,000 |
Technology | CMOS |
Die | 105.68 mm² |
Word Size | 32 bit |
Cores | 1 |
Threads | 1 |
Max Memory | 4 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Vcore | 1.40 V ± 0.1 V |
VI/O | 2.5 V ± 0.25 V |
TDP | 25 W |
Tcase | 0 °C – 95 °C |
Tstorage | -40 °C – 100 °C |
The Mobile Duron 850 based on the Morgan (Camaro) core was a 32-bit x86 microprocessor developed by AMD and introduced in early 2001. This model was part of the second generation of the Duron family. Designed based on AMD's K7 on a 180 nm process, this MPU operated at 800 MHz with a bus capable of 200 MT/s with a max TDP of 25 W.
Cache[edit]
- Main article: K7 § Cache
Cache Info [Edit Values] | ||
L1I$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
L1D$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
L2$ | 64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB |
1x64 KiB 16-way set associative |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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- Halt State
- Sleep State
Documents[edit]
DataSheet[edit]
- Mobile AMD Duron Processor Model 7 Data Sheet; Publication # 24068; Rev: F; Issue Date: December 2001.
See also[edit]
Facts about "Duron 850 (Camaro) - AMD"
has feature | Halt State + and Sleep State + |
l1d$ description | 2-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |