Semiconductor & Computer Engineering
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Difference between revisions of "amd/k6-iii+/amd-k6-iiie+-400acr"
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{{amd title|AMD-K6-IIIE+/400ACR}} | {{amd title|AMD-K6-IIIE+/400ACR}} | ||
| − | {{ | + | {{chip |
| name = AMD-K6-IIIE+/400ACR | | name = AMD-K6-IIIE+/400ACR | ||
| no image = Yes | | no image = Yes | ||
| Line 10: | Line 10: | ||
| model number = AMD-K6-IIIE+/400ACR | | model number = AMD-K6-IIIE+/400ACR | ||
| part number = AMD-K6-IIIE+/400ACR | | part number = AMD-K6-IIIE+/400ACR | ||
| − | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Embedded | | market = Embedded | ||
| first announced = September 25, 2000 | | first announced = September 25, 2000 | ||
| Line 109: | Line 109: | ||
== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| − | | mmx | + | |real=No |
| − | | emmx | + | |protected=No |
| − | | 3dnow | + | |smm=No |
| − | | e3dnow | + | |fpu=No |
| − | | pownow | + | |x8616=No |
| + | |x8632=No | ||
| + | |x8664=No | ||
| + | |nx=No | ||
| + | |mmx=Yes | ||
| + | |emmx=No | ||
| + | |sse=No | ||
| + | |sse2=No | ||
| + | |sse3=No | ||
| + | |ssse3=No | ||
| + | |sse41=No | ||
| + | |sse42=No | ||
| + | |sse4a=No | ||
| + | |avx=No | ||
| + | |avx2=No | ||
| + | |avx512f=No | ||
| + | |avx512cd=No | ||
| + | |avx512er=No | ||
| + | |avx512pf=No | ||
| + | |avx512bw=No | ||
| + | |avx512dq=No | ||
| + | |avx512vl=No | ||
| + | |avx512ifma=No | ||
| + | |avx512vbmi=No | ||
| + | |avx5124fmaps=No | ||
| + | |avx5124vnniw=No | ||
| + | |avx512vpopcntdq=No | ||
| + | |abm=No | ||
| + | |tbm=No | ||
| + | |bmi1=No | ||
| + | |bmi2=No | ||
| + | |fma3=No | ||
| + | |fma4=No | ||
| + | |aes=No | ||
| + | |rdrand=No | ||
| + | |sha=No | ||
| + | |xop=No | ||
| + | |adx=No | ||
| + | |clmul=No | ||
| + | |f16c=No | ||
| + | |tbt1=No | ||
| + | |tbt2=No | ||
| + | |tbmt3=No | ||
| + | |bpt=No | ||
| + | |eist=No | ||
| + | |sst=No | ||
| + | |flex=No | ||
| + | |fastmem=No | ||
| + | |ivmd=No | ||
| + | |intelnodecontroller=No | ||
| + | |intelnode=No | ||
| + | |kpt=No | ||
| + | |ptt=No | ||
| + | |intelrunsure=No | ||
| + | |mbe=No | ||
| + | |isrt=No | ||
| + | |sba=No | ||
| + | |mwt=No | ||
| + | |sipp=No | ||
| + | |att=No | ||
| + | |ipt=No | ||
| + | |tsx=No | ||
| + | |txt=No | ||
| + | |ht=No | ||
| + | |vpro=No | ||
| + | |vtx=No | ||
| + | |vtd=No | ||
| + | |ept=No | ||
| + | |mpx=No | ||
| + | |sgx=No | ||
| + | |securekey=No | ||
| + | |osguard=No | ||
| + | |intqat=No | ||
| + | |3dnow=Yes | ||
| + | |e3dnow=Yes | ||
| + | |smartmp=No | ||
| + | |powernow=No | ||
| + | |amdvi=No | ||
| + | |amdv=No | ||
| + | |amdsme=No | ||
| + | |amdtsme=No | ||
| + | |amdsev=No | ||
| + | |rvi=No | ||
| + | |smt=No | ||
| + | |sensemi=No | ||
| + | |xfr=No | ||
| + | |xfr2=No | ||
| + | |mxfr=No | ||
| + | |amdpb=No | ||
| + | |amdpb2=No | ||
| + | |amdpbod=No | ||
| + | |pownow=Yes | ||
}} | }} | ||
* Auto-power down state | * Auto-power down state | ||
* Stop clock state | * Stop clock state | ||
* Halt state | * Halt state | ||
Latest revision as of 02:30, 26 October 2018
| Edit Values | |
| AMD-K6-IIIE+/400ACR | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | AMD-K6-IIIE+/400ACR |
| Part Number | AMD-K6-IIIE+/400ACR |
| Market | Embedded |
| Introduction | September 25, 2000 (announced) September 25, 2000 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | K6-III+ |
| Series | K6-III+ Embedded |
| Frequency | 399.99 MHz |
| Bus type | FSB |
| Bus speed | 99.99 MHz |
| Bus rate | 99.99 MT/s |
| Clock multiplier | 4 |
| CPUID | 5D0 |
| Microarchitecture | |
| Microarchitecture | K6-III |
| Platform | Super 7 |
| Core Family | 5 |
| Core Model | 13 |
| Core Stepping | 0, 1, 2, 3 |
| Process | 0.18 µm |
| Transistors | 21,400,000 |
| Technology | CMOS |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Vcore | 2.0 V ± 0.1 V |
| VI/O | 3.3675 V ± 7% |
| TDP | 9.5 W |
| Tcase | 0 °C – 70 °C |
| Tstorage | -65 °C – 150 °C |
AMD-K6-IIIE+/400ACR is a 32-bit x86 embedded microprocessor designed by AMD and introduced in late 2000. This MPU which was manufactured on a 0.18 µm process, based on K6-III microarchitecture, operated at 400 MHz with a bus of 100 MHz and a multiplier of 4. This chip had a TDP of 9.5 W.
Cache[edit]
- Main article: K6-III § Cache
L3$ can be 512 KiB to 2 MiB, depending on manufacturer and motherboard model. L3$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
| L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
| L2$ | 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB |
1x256 KiB 4-way set associative (shared) |
Graphics[edit]
This processors has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
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- Auto-power down state
- Stop clock state
- Halt state
Facts about "AMD-K6-IIIE+/400ACR - AMD"
| l1d$ description | 2-way set associative + |
| l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |