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{{pezy title|PEZY-SC3}}
 
{{pezy title|PEZY-SC3}}
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{{mpu
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{{chip
 
|future=Yes
 
|future=Yes
 
|name=PEZY-SC3
 
|name=PEZY-SC3
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|market=Supercomputer
 
|market=Supercomputer
 
|first announced=2016
 
|first announced=2016
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|first launched=2018
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|first launched=2019
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|frequency=1,333 MHz
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|family=PEZY-SCx
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|frequency=1,333.333 MHz
 
|process=7 nm
 
|process=7 nm
 
|technology=CMOS
 
|technology=CMOS
 
|die area=700 mm²
 
|die area=700 mm²
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|core count=8,096
+
|core count=8,192
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|thread count=65,536
 
|power=400 W
 
|power=400 W
 
|v core=0.65 V
 
|v core=0.65 V
 
}}
 
}}
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'''PEZY-SC3''' ('''PEZY Super Computer 3''') is fourth generation [[many-core microprocessor]] planned by [[PEZY]]. The SC3 incorporates 8,096 cores, four times as many cores as its predecessor.
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'''PEZY-SC3''' ('''PEZY Super Computer 3''') is a fourth generation [[many-core microprocessor]] developed by [[PEZY]] set to be introduced in late 2019. This chip, which is planned to operate at 1.3 GHz, will incorporate 8,192 cores and dissipate 400 W. The PEZY-SC3 will power the [[ZettaScaler]]-3.x series of supercomputers.
  
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Planned to be fabricated on TSMC's [[7 nm process]], PEZY-SC3 operates at 1.33 GHz and consume around 400 W while delivering performance in the order of 87.2 TFLOPS (HP), 43.6 TFLOPS (SP), and 21.8 TFLOPS (DP).
 
  
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{{unknown features}}
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 +
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== Overview ==
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The SC3 will be introduced by [[PEZY]] along with their third-generation [[ZettaScaler]]-3.0 supercomputer series. The SC3 is set to incorporate 8,192 cores along with 8-way [[simultaneous multithreading|SMT]] support for a total of 65,536 threads, four times as many cores as {{\\|PEZY-SC2|its predecessor}}.
  
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{{unknown features}}
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Operating at 1.3 GHz, the PEZY-SC3 will have a peak performance of 43.69 [[TFLOPS]] (single-precision) and 21.845 TFLOPS (double-precision) while consuming around 400 Watts. The PEZY-SC3 is expected to be manufactured on [[TSMC]]'s [[7 nm process]].
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{{#set:
 +
| peak flops (half-precision)  = {{#expr:1333333333 * 8 * 8192}} FLOPS
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| peak flops (single-precision) = {{#expr:1333333333 * 4 * 8192}} FLOPS
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| peak flops (double-precision) = {{#expr:1333333333 * 2 * 8192}} FLOPS
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}}
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== Cache ==
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{{empty section}}
  
 
== Memory controller ==
 
== Memory controller ==
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For main memory, the PEZY-SC3 supports 4 channels of 64-bit DDR4-3600 memory with ECC support for a total aggregated bandwidth of 107.3 GiB/s
 
{{memory controller
 
{{memory controller
 
|type=DDR4-3600
 
|type=DDR4-3600
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|controllers=4
 
|controllers=4
 
|channels=4
 
|channels=4
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|width=64 bit
 
|max bandwidth=107.3 GiB/s
 
|max bandwidth=107.3 GiB/s
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|bandwidth schan=26.82 GiB/s
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|bandwidth dchan=53.64 GiB/s
 
|bandwidth qchan=107.3 GiB/s
 
|bandwidth qchan=107.3 GiB/s
 
}}
 
}}
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In addition to main memory bandwidth, the PEZY-SC3 supports Wide-IO with a width of 2,048 bit, twice of the {{\\|PEZY-SC2|SC2}}. As with the SC2, the SC3 will use [[ThruChip Interface]] (TCI) interfaces in order to communicate with the TCI-DRAM chips. This chip incorporates 8 interfaces, operating at 3 GHz for a bandwidth of 1.525 TB/s per interface for a total aggregated bandwidth of 12.2 TB/s - over 5.8 the bandwidth of its predecessor.
  
 
{{memory controller
 
{{memory controller
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|wide-io clock=2,000 MHz
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|wide-io clock=3,000 MHz
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|wide-io width=3,072 bit
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|wide-io width=2,048 bit
 
|channels=8
 
|channels=8
 
|max bandwidth=11.18 TiB/s
 
|max bandwidth=11.18 TiB/s
 
}}
 
}}
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== Expansions ==
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With the SC3, PEZY plans to replace {{\\|PEZY-SC2|the previous}} PCIe interface with a custom optics interface featuring 128 lanes supporting a bandwidth of 256 GB/s.

Latest revision as of 11:41, 28 September 2019

Edit Values
PEZY-SC3
General Info
DesignerPEZY
ManufacturerTSMC
Model NumberPEZY-SC3
MarketSupercomputer
Introduction2016 (announced)
2019 (launched)
General Specs
FamilyPEZY-SCx
Frequency1,333.333 MHz
Microarchitecture
Process7 nm
TechnologyCMOS
Die700 mm²
Cores8,192
Threads65,536
Electrical
Power dissipation400 W
Vcore0.65 V

PEZY-SC3 (PEZY Super Computer 3) is a fourth generation many-core microprocessor developed by PEZY set to be introduced in late 2019. This chip, which is planned to operate at 1.3 GHz, will incorporate 8,192 cores and dissipate 400 W. The PEZY-SC3 will power the ZettaScaler-3.x series of supercomputers.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Overview[edit]

The SC3 will be introduced by PEZY along with their third-generation ZettaScaler-3.0 supercomputer series. The SC3 is set to incorporate 8,192 cores along with 8-way SMT support for a total of 65,536 threads, four times as many cores as its predecessor.

Operating at 1.3 GHz, the PEZY-SC3 will have a peak performance of 43.69 TFLOPS (single-precision) and 21.845 TFLOPS (double-precision) while consuming around 400 Watts. The PEZY-SC3 is expected to be manufactured on TSMC's 7 nm process.

Cache[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory controller[edit]

For main memory, the PEZY-SC3 supports 4 channels of 64-bit DDR4-3600 memory with ECC support for a total aggregated bandwidth of 107.3 GiB/s

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-3600
Supports ECCYes
Controllers4
Channels4
Width64 bit
Max Bandwidth107.3 GiB/s
109,875.2 MiB/s
115.212 GB/s
115,212.498 MB/s
0.105 TiB/s
0.115 TB/s
Bandwidth
Single 26.82 GiB/s
Double 53.64 GiB/s
Quad 107.3 GiB/s

In addition to main memory bandwidth, the PEZY-SC3 supports Wide-IO with a width of 2,048 bit, twice of the SC2. As with the SC2, the SC3 will use ThruChip Interface (TCI) interfaces in order to communicate with the TCI-DRAM chips. This chip incorporates 8 interfaces, operating at 3 GHz for a bandwidth of 1.525 TB/s per interface for a total aggregated bandwidth of 12.2 TB/s - over 5.8 the bandwidth of its predecessor.

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
MemoryWide I/O
Rate3,000 MHz
Width2,048 bit
Channels8
Max Bandwidth11.18 TiB/s
11,448.32 GiB/s
11,723,079.68 MiB/s
12,292.54 GB/s
12,292,539.999 MB/s
12.293 TB/s

Expansions[edit]

With the SC3, PEZY plans to replace the previous PCIe interface with a custom optics interface featuring 128 lanes supporting a bandwidth of 256 GB/s.

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Facts about "PEZY-SC3 - PEZY"
RDF feed
has ecc memory supporttrue + and false +
max memory bandwidth107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + and 11,448.32 GiB/s (11,723,079.68 MiB/s, 12,292.54 GB/s, 12,292,539.999 MB/s, 11.18 TiB/s, 12.293 TB/s) +
max memory channels4 + and 8 +
supported memory typeDDR4-3600 +