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Difference between revisions of "amd/epyc/7351p"
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{{amd title|EPYC 7351P}} | {{amd title|EPYC 7351P}} | ||
− | {{ | + | {{chip |
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|name=EPYC 7351P | |name=EPYC 7351P | ||
|no image=Yes | |no image=Yes | ||
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|manufacturer=GlobalFoundries | |manufacturer=GlobalFoundries | ||
|model number=7351P | |model number=7351P | ||
+ | |part number=PS735PBEVGPAF | ||
|market=Server | |market=Server | ||
|first announced=June 20, 2017 | |first announced=June 20, 2017 | ||
+ | |first launched=June 20, 2017 | ||
+ | |release price=$750 | ||
|family=EPYC | |family=EPYC | ||
|series=7000 | |series=7000 | ||
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|turbo frequency15=2,900 MHz | |turbo frequency15=2,900 MHz | ||
|turbo frequency16=2,900 MHz | |turbo frequency16=2,900 MHz | ||
− | |||
− | |||
|clock multiplier=24 | |clock multiplier=24 | ||
|isa=x86-64 | |isa=x86-64 | ||
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|microarch=Zen | |microarch=Zen | ||
|core name=Naples | |core name=Naples | ||
+ | |core family=23 | ||
+ | |core model=1 | ||
+ | |core stepping=B2 | ||
|process=14 nm | |process=14 nm | ||
|transistors=19,200,000,000 | |transistors=19,200,000,000 | ||
|technology=CMOS | |technology=CMOS | ||
− | |die area= | + | |die area=213 mm² |
− | |||
− | |||
|mcp=Yes | |mcp=Yes | ||
|die count=4 | |die count=4 | ||
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|tdp=155 W | |tdp=155 W | ||
|tdp 2=170 W | |tdp 2=170 W | ||
− | |package | + | |tcase min=0 °C |
+ | |tcase max=85 °C | ||
+ | |package name 1=amd,socket_sp3 | ||
}} | }} | ||
'''EPYC 7351P''' is a {{arch|64}} [[16-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7351P has a base frequency of 2.4 GHz with a turbo frequency of 2.9 GHz for all cores. This chip has a TDP of 170 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory. The TDP is slightly lower at 155 W if DDR4-2400 is used instead. | '''EPYC 7351P''' is a {{arch|64}} [[16-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7351P has a base frequency of 2.4 GHz with a turbo frequency of 2.9 GHz for all cores. This chip has a TDP of 170 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory. The TDP is slightly lower at 155 W if DDR4-2400 is used instead. | ||
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|ecc=Yes | |ecc=Yes | ||
|max mem=2 TiB | |max mem=2 TiB | ||
− | |controllers= | + | |controllers=8 |
|channels=8 | |channels=8 | ||
|max bandwidth=158.95 GiB/s | |max bandwidth=158.95 GiB/s | ||
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|avx=Yes | |avx=Yes | ||
|avx2=Yes | |avx2=Yes | ||
− | + | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No | ||
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|amdvi=Yes | |amdvi=Yes | ||
|amdv=Yes | |amdv=Yes | ||
+ | |amdsme=Yes | ||
+ | |amdtsme=Yes | ||
+ | |amdsev=Yes | ||
|rvi=No | |rvi=No | ||
|smt=Yes | |smt=Yes |
Latest revision as of 11:24, 18 March 2023
Edit Values | |
EPYC 7351P | |
General Info | |
Designer | AMD |
Manufacturer | GlobalFoundries |
Model Number | 7351P |
Part Number | PS735PBEVGPAF |
Market | Server |
Introduction | June 20, 2017 (announced) June 20, 2017 (launched) |
Release Price | $750 |
Shop | Amazon |
General Specs | |
Family | EPYC |
Series | 7000 |
Locked | No |
Frequency | 2,400 MHz |
Turbo Frequency | 2,900 MHz (1 core), 2,900 MHz (2 cores), 2,900 MHz (3 cores), 2,900 MHz (4 cores), 2,900 MHz (5 cores), 2,900 MHz (6 cores), 2,900 MHz (7 cores), 2,900 MHz (8 cores), 2,900 MHz (9 cores), 2,900 MHz (10 cores), 2,900 MHz (11 cores), 2,900 MHz (12 cores), 2,900 MHz (13 cores), 2,900 MHz (14 cores), 2,900 MHz (15 cores), 2,900 MHz (16 cores) |
Clock multiplier | 24 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen |
Core Name | Naples |
Core Family | 23 |
Core Model | 1 |
Core Stepping | B2 |
Process | 14 nm |
Transistors | 19,200,000,000 |
Technology | CMOS |
Die | 213 mm² |
MCP | Yes (4 dies) |
Word Size | 64 bit |
Cores | 16 |
Threads | 32 |
Max Memory | 2 TiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 155 W, 170 W |
Tcase | 0 °C – 85 °C |
Packaging | |
Package | SP3, FCLGA-4094 (FC-OLGA) |
Dimension | 75.4 mm × 58.5 mm × 6.26 mm |
Pitch | 0.87 mm × 1 mm |
Contacts | 4094 |
Socket | SP3, LGA-4094 |
EPYC 7351P is a 64-bit 16-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7351P has a base frequency of 2.4 GHz with a turbo frequency of 2.9 GHz for all cores. This chip has a TDP of 170 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory. The TDP is slightly lower at 155 W if DDR4-2400 is used instead.
Contents
Cache[edit]
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
The EPYC 7351P has 128 Gen 3 PCIe lanes.
Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
Facts about "EPYC 7351P - AMD"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | EPYC 7351P - AMD#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd sensemi technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + |
max memory bandwidth | 158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) + |
max memory channels | 8 + |
max pcie lanes | 128 + |
supported memory type | DDR4-2666 + and DDR4-2400 + |