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Difference between revisions of "amd/epyc/7601"
< amd‎ | epyc

(Created page with "{{amd title|EPYC 7601}} {{mpu |name=EPYC 7601 |no image=Yes |designer=AMD |manufacturer=GlobalFoundries |model number=7601 |market=Server |first announced=June 20, 2017 |famil...")
 
(Replaced package module by package name.)
 
(22 intermediate revisions by 6 users not shown)
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{{amd title|EPYC 7601}}
 
{{amd title|EPYC 7601}}
−
{{mpu
+
{{chip
 
|name=EPYC 7601
 
|name=EPYC 7601
 
|no image=Yes
 
|no image=Yes
Line 6: Line 6:
 
|manufacturer=GlobalFoundries
 
|manufacturer=GlobalFoundries
 
|model number=7601
 
|model number=7601
 +
|part number=PS7601BDVIHAF
 
|market=Server
 
|market=Server
 
|first announced=June 20, 2017
 
|first announced=June 20, 2017
 +
|first launched=June 20, 2017
 +
|release price=$4,200
 
|family=EPYC
 
|family=EPYC
 
|series=7000
 
|series=7000
Line 13: Line 16:
 
|frequency=2,200 MHz
 
|frequency=2,200 MHz
 
|turbo frequency1=3,200 MHz
 
|turbo frequency1=3,200 MHz
−
|bus links=4
+
|turbo frequency2=3,200 MHz
−
|bus rate=8 GT/s
+
|turbo frequency3=3,200 MHz
 +
|turbo frequency4=3,200 MHz
 +
|turbo frequency5=3,200 MHz
 +
|turbo frequency6=3,200 MHz
 +
|turbo frequency7=3,200 MHz
 +
|turbo frequency8=3,200 MHz
 +
|turbo frequency9=3,200 MHz
 +
|turbo frequency10=3,200 MHz
 +
|turbo frequency11=3,200 MHz
 +
|turbo frequency12=3,200 MHz
 +
|turbo frequency13=2,700 MHz
 +
|turbo frequency14=2,700 MHz
 +
|turbo frequency15=2,700 MHz
 +
|turbo frequency16=2,700 MHz
 +
|turbo frequency17=2,700 MHz
 +
|turbo frequency18=2,700 MHz
 +
|turbo frequency19=2,700 MHz
 +
|turbo frequency20=2,700 MHz
 +
|turbo frequency21=2,700 MHz
 +
|turbo frequency22=2,700 MHz
 +
|turbo frequency23=2,700 MHz
 +
|turbo frequency24=2,700 MHz
 +
|turbo frequency25=2,700 MHz
 +
|turbo frequency26=2,700 MHz
 +
|turbo frequency27=2,700 MHz
 +
|turbo frequency28=2,700 MHz
 +
|turbo frequency29=2,700 MHz
 +
|turbo frequency30=2,700 MHz
 +
|turbo frequency31=2,700 MHz
 +
|turbo frequency32=2,700 MHz
 
|clock multiplier=22
 
|clock multiplier=22
 
|isa=x86-64
 
|isa=x86-64
Line 20: Line 52:
 
|microarch=Zen
 
|microarch=Zen
 
|core name=Naples
 
|core name=Naples
 +
|core family=23
 +
|core model=1
 +
|core stepping=B2
 
|process=14 nm
 
|process=14 nm
 
|transistors=19,200,000,000
 
|transistors=19,200,000,000
 
|technology=CMOS
 
|technology=CMOS
−
|die area=195.228 mm²
+
|die area=213 mm²
−
|die length=8.87 mm
 
−
|die width=22.01 mm
 
 
|mcp=Yes
 
|mcp=Yes
 
|die count=4
 
|die count=4
Line 34: Line 67:
 
|max memory=2 TiB
 
|max memory=2 TiB
 
|tdp=180W
 
|tdp=180W
−
|package module 1={{packages/amd/socket sp3}}
+
|tcase min=0 °C
 +
|tcase max=81 °C
 +
|package name 1=amd,socket_sp3
 +
}}
 +
'''EPYC 7601''' is a dual-socket {{arch|64}} [[32-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7601 has a base frequency of 2.2 GHz with a turbo frequency of 3.2 GHz for up to 12 active cores. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket.
 +
 
 +
 
 +
{{unknown features}}
 +
 
 +
 
 +
== Cache ==
 +
{{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}}
 +
{{cache size
 +
|l1 cache=3 MiB
 +
|l1i cache=2 MiB
 +
|l1i break=32x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=1 MiB
 +
|l1d break=32x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=16 MiB
 +
|l2 break=32x512 KiB
 +
|l2 desc=8-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=64 MiB
 +
|l3 break=8x8 MiB
 +
|l3 desc=16-way set associative
 +
|l3 policy=write-back
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2666
 +
|ecc=Yes
 +
|max mem=2 TiB
 +
|controllers=8
 +
|channels=8
 +
|max bandwidth=158.95 GiB/s
 +
|bandwidth schan=19.89 GiB/s
 +
|bandwidth dchan=39.72 GiB/s
 +
|bandwidth qchan=79.47 GiB/s
 +
|bandwidth ochan=158.95 GiB/s
 +
|bandwidth hchan=119.21 GiB/s
 +
}}
 +
 
 +
In a dual-socket configuration, the maximum supported memory doubles to 4 TiB along with the maximum theoretical bandwidth of 317.9 GiB/s.
 +
 
 +
== Expansions ==
 +
The EPYC 7601 has 128 Gen 3 PCIe lanes. In a dual-socket configuration, half of the lanes are used for inter-processor communication, so again 128 lanes are available for expansions.
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 128
 +
| pcie config        = 8x16
 +
| pcie config 2      = 32x4
 +
| sata revision      =
 +
| sata ports        =
 +
| usb revision      =
 +
| usb revision 2    =
 +
| usb ports          =
 +
| usb rate          =
 +
| uart              =
 +
| uart ports        =
 +
| gp io              =
 +
}}
 +
 
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=Yes
 +
|avx=Yes
 +
|avx2=Yes
 +
 
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=Yes
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=No
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=No
 +
|vpro=No
 +
|vtx=No
 +
|vtd=No
 +
|ept=No
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=Yes
 +
|amdv=Yes
 +
|amdsme=Yes
 +
|amdtsme=Yes
 +
|amdsev=Yes
 +
|rvi=No
 +
|smt=Yes
 +
|sensemi=Yes
 +
|xfr=No
 +
}}
 +
 
 +
== Benchmarks ==
 +
{{benchmarks main
 +
|
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00334.html|test_timestamp=2017-10-24 18:28:59-0400|chip_count=2|core_count=64|copies_count=128|vendor=HPE|system=ProLiant DL385 Gen10 (2.20 GHz, AMD EPYC 7601)|SPECrate2017_int_base=271|SPECrate2017_int_peak=299}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00366.html|test_timestamp=2017-10-25 06:03:04-0400|chip_count=2|core_count=64|copies_count=128|vendor=HPE|system=ProLiant DL385 Gen10 (2.20 GHz, AMD EPYC 7601)|SPECrate2017_fp_base=257|SPECrate2017_fp_peak=270}}
 
}}
 
}}
−
'''EPYC 7601''' is a dual-socket {{arch|64}} [[32-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7601 has a base frequency of 2.2 GHz with a turbo frequency of 3.2 GHz for a single active core. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket.
 

Latest revision as of 11:30, 18 March 2023

Edit Values
EPYC 7601
General Info
DesignerAMD
ManufacturerGlobalFoundries
Model Number7601
Part NumberPS7601BDVIHAF
MarketServer
IntroductionJune 20, 2017 (announced)
June 20, 2017 (launched)
Release Price$4,200
ShopAmazon
General Specs
FamilyEPYC
Series7000
LockedNo
Frequency2,200 MHz
Turbo Frequency3,200 MHz (1 core),
3,200 MHz (2 cores),
3,200 MHz (3 cores),
3,200 MHz (4 cores),
3,200 MHz (5 cores),
3,200 MHz (6 cores),
3,200 MHz (7 cores),
3,200 MHz (8 cores),
3,200 MHz (9 cores),
3,200 MHz (10 cores),
3,200 MHz (11 cores),
3,200 MHz (12 cores),
2,700 MHz (13 cores),
2,700 MHz (14 cores),
2,700 MHz (15 cores),
2,700 MHz (16 cores),
2,700 MHz (17 cores),
2,700 MHz (18 cores),
2,700 MHz (19 cores),
2,700 MHz (20 cores),
2,700 MHz (21 cores),
2,700 MHz (22 cores),
2,700 MHz (23 cores),
2,700 MHz (24 cores),
2,700 MHz (25 cores),
2,700 MHz (26 cores),
2,700 MHz (27 cores),
2,700 MHz (28 cores),
2,700 MHz (29 cores),
2,700 MHz (30 cores),
2,700 MHz (31 cores),
2,700 MHz (32 cores)
Clock multiplier22
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen
Core NameNaples
Core Family23
Core Model1
Core SteppingB2
Process14 nm
Transistors19,200,000,000
TechnologyCMOS
Die213 mm²
MCPYes (4 dies)
Word Size64 bit
Cores32
Threads64
Max Memory2 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
TDP180W
Tcase0 °C – 81 °C
Packaging
PackageSP3, FCLGA-4094 (FC-OLGA)
Dimension75.4 mm × 58.5 mm × 6.26 mm
Pitch0.87 mm × 1 mm
Contacts4094
SocketSP3, LGA-4094

EPYC 7601 is a dual-socket 64-bit 32-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7601 has a base frequency of 2.2 GHz with a turbo frequency of 3.2 GHz for up to 12 active cores. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache[edit]

Main article: Zen § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$3 MiB
3,072 KiB
3,145,728 B
L1I$2 MiB
2,048 KiB
2,097,152 B
32x64 KiB4-way set associative 
L1D$1 MiB
1,024 KiB
1,048,576 B
32x32 KiB8-way set associativewrite-back
L2$16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
  32x512 KiB8-way set associativewrite-back
L3$64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
  8x8 MiB16-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem2 TiB
Controllers8
Channels8
Max Bandwidth158.95 GiB/s
162,764.8 MiB/s
170.671 GB/s
170,671.263 MB/s
0.155 TiB/s
0.171 TB/s
Bandwidth
Single 19.89 GiB/s
Double 39.72 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s
Octa 158.95 GiB/s

In a dual-socket configuration, the maximum supported memory doubles to 4 TiB along with the maximum theoretical bandwidth of 317.9 GiB/s.

Expansions[edit]

The EPYC 7601 has 128 Gen 3 PCIe lanes. In a dual-socket configuration, half of the lanes are used for inter-processor communication, so again 128 lanes are available for expansions.

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes128
Configs8x16, 32x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SMESecure Memory Encryption
TSMETransparent SME
SEVSecure Encrypted Virtualization
SenseMISenseMI Technology

Benchmarks[edit]

[Edit Benchmarks]

Test: SPEC CPU2017
Tested: 2017-10-24 18:28:59-0400
Chips: 2, Cores: 64, Copies: 128
benchmarks.svg
Vendor: HPE
System: ProLiant DL385 Gen10 (2.20 GHz, AMD EPYC 7601)
SPECrate2017_int_base: 271
SPECrate2017_int_peak: 299
Test: SPEC CPU2017
Tested: 2017-10-25 06:03:04-0400
Chips: 2, Cores: 64, Copies: 128
benchmarks.svg
Vendor: HPE
System: ProLiant DL385 Gen10 (2.20 GHz, AMD EPYC 7601)
SPECrate2017_fp_base: 257
SPECrate2017_fp_peak: 270
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc/7601&oldid=101300"
Facts about "EPYC 7601 - AMD"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
EPYC 7601 - AMD#io +, EPYC 7601 - AMD + and EPYC 7601 - AMD +
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
clock multiplier22 +
core count32 +
core family23 +
core model1 +
core nameNaples +
core steppingB2 +
designerAMD +
die area213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) +
die count4 +
familyEPYC +
first announcedJune 20, 2017 +
first launchedJune 20, 2017 +
full page nameamd/epyc/7601 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd secure encrypted virtualization technologytrue +
has amd secure memory encryption technologytrue +
has amd sensemi technologytrue +
has amd transparent secure memory encryption technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has locked clock multiplierfalse +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size3,072 KiB (3,145,728 B, 3 MiB) +
l1d$ description8-way set associative +
l1d$ size1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ description4-way set associative +
l1i$ size2,048 KiB (2,097,152 B, 2 MiB) +
l2$ description8-way set associative +
l2$ size16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
l3$ description16-way set associative +
l3$ size64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldateJune 20, 2017 +
manufacturerGlobalFoundries +
market segmentServer +
max case temperature354.15 K (81 °C, 177.8 °F, 637.47 °R) +
max cpu count2 +
max memory2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) +
max memory channels8 +
max pcie lanes128 +
microarchitectureZen +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number7601 +
nameEPYC 7601 +
packageSP3 + and FCLGA-4094 +
part numberPS7601BDVIHAF +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 4,200.00 (€ 3,780.00, £ 3,402.00, ¥ 433,986.00) +
series7000 +
smp max ways2 +
socketSP3 + and LGA-4094 +
supported memory typeDDR4-2666 +
tdp180 W (180,000 mW, 0.241 hp, 0.18 kW) +
technologyCMOS +
thread count64 +
transistor count19,200,000,000 +
turbo frequency (10 cores)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (11 cores)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (12 cores)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (13 cores)2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (14 cores)2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (15 cores)2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (16 cores)2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (17 cores)2,700 MHz +
turbo frequency (18 cores)2,700 MHz +
turbo frequency (19 cores)2,700 MHz +
turbo frequency (1 core)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (20 cores)2,700 MHz +
turbo frequency (21 cores)2,700 MHz +
turbo frequency (22 cores)2,700 MHz +
turbo frequency (23 cores)2,700 MHz +
turbo frequency (24 cores)2,700 MHz +
turbo frequency (25 cores)2,700 MHz +
turbo frequency (26 cores)2,700 MHz +
turbo frequency (27 cores)2,700 MHz +
turbo frequency (28 cores)2,700 MHz +
turbo frequency (29 cores)2,700 MHz +
turbo frequency (2 cores)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (30 cores)2,700 MHz +
turbo frequency (31 cores)2,700 MHz +
turbo frequency (32 cores)2,700 MHz +
turbo frequency (3 cores)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (4 cores)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (5 cores)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (6 cores)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (7 cores)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (8 cores)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (9 cores)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +