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Difference between revisions of "dec/microarchitectures/alpha 21164"
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|designer=DEC
 
|designer=DEC
 
|manufacturer=DEC
 
|manufacturer=DEC
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|manufacturer 2=Samsung
 
|introduction=January, 1995
 
|introduction=January, 1995
 
|process=0.5 µm
 
|process=0.5 µm
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|renaming=No
 
|renaming=No
 
|stages min=7
 
|stages min=7
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|stages max=9
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|stages max=12
 
|decode=4-way
 
|decode=4-way
 
|isa=Alpha
 
|isa=Alpha
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}}
 
'''Alpha 21164''' was an [[Alpha]] microarchitecture designed by [[DEC]] and introduced in 1995 as a successor to the {{\\|Alpha 21064}} architecture.
 
'''Alpha 21164''' was an [[Alpha]] microarchitecture designed by [[DEC]] and introduced in 1995 as a successor to the {{\\|Alpha 21064}} architecture.
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== History ==
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{{empty section}}
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== Process Technology ==
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{{see also|0.5 µm process}}
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{{empty section}}
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== Architecture ==
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{{empty section}}
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== Die ==
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* 30.5W at 366MHz
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* 9,300,000 transistors
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** ????? cache
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** ????? logic
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* [[0.5 µm]] 4 metal layers
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* 16.5 mm x 18.1 mm
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* 298.65 mm² die size
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* PGA-499 package
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** 294 signal pins
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** 205 power/ground rail pins
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: [[File:alpha 21164 die shot.png|650px]]
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: [[File:alpha 21164 die shot (annotated).png|650px]]
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== References ==
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* Edmondson, John H., et al. "Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor." Digital Technical Journal 7.1 (1995).
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* Bowhill, William J., et al. "A 300 MHz 64 b quad-issue CMOS RISC microprocessor." Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International. IEEE, 1995.

Latest revision as of 10:52, 27 November 2020

Edit Values
Alpha 21164 µarch
General Info
Arch TypeCPU
DesignerDEC
ManufacturerDEC, Samsung
IntroductionJanuary, 1995
Process0.5 µm
Core Configs1
Pipeline
TypeSuperscalar
OoOENo
SpeculativeYes
Reg RenamingNo
Stages7-12
Decode4-way
Instructions
ISAAlpha
Cache
L1I Cache8 KiB/core
direct-mapped
L1D Cache8 KiB/core
direct-mapped
L2 Cache96 KiB/core
3-way set associative
L3 Cache1-64 MiB/motherboard
direct-mapped
Succession

Alpha 21164 was an Alpha microarchitecture designed by DEC and introduced in 1995 as a successor to the Alpha 21064 architecture.

History[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Process Technology[edit]

See also: 0.5 µm process
New text document.svg This section is empty; you can help add the missing info by editing this page.

Architecture[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Die[edit]

  • 30.5W at 366MHz
  • 9,300,000 transistors
    •  ????? cache
    •  ????? logic
  • 0.5 µm 4 metal layers
  • 16.5 mm x 18.1 mm
  • 298.65 mm² die size
  • PGA-499 package
    • 294 signal pins
    • 205 power/ground rail pins


alpha 21164 die shot.png


alpha 21164 die shot (annotated).png

References[edit]

  • Edmondson, John H., et al. "Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor." Digital Technical Journal 7.1 (1995).
  • Bowhill, William J., et al. "A 300 MHz 64 b quad-issue CMOS RISC microprocessor." Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International. IEEE, 1995.
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Facts about "Alpha 21164 - Microarchitectures - DEC"
RDF feed
codenameAlpha 21164 +
core count1 +
designerDEC +
first launchedJanuary 1995 +
full page namedec/microarchitectures/alpha 21164 +
instance ofmicroarchitecture +
instruction set architectureAlpha +
manufacturerDEC + and Samsung +
microarchitecture typeCPU +
nameAlpha 21164 +
pipeline stages (max)12 +
pipeline stages (min)7 +
process500 nm (0.5 μm, 5.0e-4 mm) +