Semiconductor & Computer Engineering
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Difference between revisions of "Template:nodes comp"
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| {{{process 1 gate len|}}} || {{#ifeq: {{{process 1 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{{process 1 gate len Δ|}}} }}<!-- | | {{{process 1 gate len|}}} || {{#ifeq: {{{process 1 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{{process 1 gate len Δ|}}} }}<!-- | ||
-->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{{process 2 gate len|}}} {{!}}{{!}} {{#ifeq: {{{process 2 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{{process 2 gate len Δ|}}} }} }}<!-- | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} {{{process 2 gate len|}}} {{!}}{{!}} {{#ifeq: {{{process 2 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{{process 2 gate len Δ|}}} }} }}<!-- | ||
| − | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{{process 3 gate len|}}} {{!}}{{!}} {{#ifeq: {{{process 3 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | | + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} {{{process 3 gate len|}}} {{!}}{{!}} {{#ifeq: {{{process 3 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{{process 3 gate len Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 gate len|}}} {{!}}{{!}} {{#ifeq: {{{process 4 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | | + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} {{{process 4 gate len|}}} {{!}}{{!}} {{#ifeq: {{{process 4 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{{process 4 gate len Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 gate len|}}} {{!}}{{!}} {{#ifeq: {{{process 5 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | | + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} {{{process 5 gate len|}}} {{!}}{{!}} {{#ifeq: {{{process 5 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{{process 5 gate len Δ|}}} }} }}<!-- |
| − | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 gate len|}}} {{!}}{{!}} {{#ifeq: {{{process 6 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | | + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} {{{process 6 gate len|}}} {{!}}{{!}} {{#ifeq: {{{process 6 gate len Δ|}}} | - | rowspan="7" style="background: #a3a3a3;" {{!}} N/A | {{{process 6 gate len Δ|}}} }} }} |
|- | |- | ||
| {{{process 1 cpp|}}} {{#ifeq: {{{process 1 cpp Δ|}}} | - | | {{!}}{{!}} {{{process 1 cpp Δ|}}} }}<!-- | | {{{process 1 cpp|}}} {{#ifeq: {{{process 1 cpp Δ|}}} | - | | {{!}}{{!}} {{{process 1 cpp Δ|}}} }}<!-- | ||
Latest revision as of 16:45, 19 March 2025
| Process Name | |
|---|---|
| 1st Production | |
| Litho- graphy |
Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Tran- sistor |
Type |
| Voltage | |
| Metal Layers | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell |
High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell |
eDRAM |
| Value | |
|---|---|