Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/microarchitectures/p5"
(→Die Shot) |
|||
| (One intermediate revision by the same user not shown) | |||
| Line 8: | Line 8: | ||
| phase-out = October, 1995 | | phase-out = October, 1995 | ||
| process = 600 nm | | process = 600 nm | ||
| + | |isa=x86-32 | ||
| succession = Yes | | succession = Yes | ||
Latest revision as of 18:34, 30 November 2017
| Edit Values | |
| P5 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | April, 1993 |
| Phase-out | October, 1995 |
| Process | 600 nm |
| Instructions | |
| ISA | x86-32 |
| Succession | |
P5 was the microarchitecture for Intel's for Pentium line of microprocessors as a successor to the 80486. Introduced in 1993, P5 was manufactured using 600 nm process. In late 1995 P5 was succeeded by P6.
Die Shot[edit]
- 600 nm process
- 3,100,000 transistors
Facts about "P5 - Microarchitectures - Intel"
| codename | P5 + |
| designer | Intel + |
| first launched | April 1993 + |
| full page name | intel/microarchitectures/p5 + |
| instance of | microarchitecture + |
| instruction set architecture | x86-32 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | P5 + |
| phase-out | October 1995 + |
| process | 600 nm (0.6 μm, 6.0e-4 mm) + |