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Difference between revisions of "intel/microarchitectures/p6"
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| process          = 350 nm
 
| process          = 350 nm
 
| process 2        = 250 nm
 
| process 2        = 250 nm
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|isa=x86-32
  
 
| succession      = Yes
 
| succession      = Yes
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| successor 2 link = intel/microarchitectures/pentium_m
 
| successor 2 link = intel/microarchitectures/pentium_m
 
}}
 
}}
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'''P6''' was the [[microarchitecture]] for [[Intel]]'s for desktops and servers as a successor to {{\\|P5}}. Introduced in 1995 and continued until 2000, P6 was fabricated using [[350 nm]] and [[250 nm]] processes. P6 was obsoleted by {{\\|NetBurst}} in late 2000.
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[[File:pentium pro processor with 1m l2 cache.jpg|right|thumb|{{intel|Pentium Pro}} processor with 1M of [[L2 cache]].]]
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'''P6''' was the [[microarchitecture]] for [[Intel]]'s for desktops and servers as a successor to {{\\|P5}}. Introduced in 1995 and continued until 2000, P6 was fabricated using [[350 nm]] and [[250 nm]] processes. P6 was made obsolete by {{\\|NetBurst}} in late 2000.
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== Codenames ==
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{{empty section}}
  
 
== Process Technology ==
 
== Process Technology ==
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P6 was manufactured on [[0.35 µm process]] initially and alter enjoyed a process shrink down to [[0.25 µm]] allowing for considerably lower voltage and higher clock speed at a smaller silicon die area. With the shrink introduced a 5th metal layer which further reduced RC delay and die area. Intel claimed channel area was reduced by 50% with the introduction of the 5th layer. The 5th layer also enabled Intel to support C4 packaging.
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P6 was manufactured on the [[0.35 µm process]] initially and later enjoyed a process shrink down to [[0.25 µm]], allowing for considerably lower voltage and higher clock speed at a smaller silicon die area. The shrink introduced a 5th metal layer which further reduced RC delay and die area. Intel claimed the channel area was reduced by 50% with the introduction of the 5th layer. The 5th layer also enabled Intel to support C4 packaging.
  
 
{| class="wikitable"
 
{| class="wikitable"
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| Interconnect Pitch || 880 nm || 640 nm || 0.73x
 
| Interconnect Pitch || 880 nm || 640 nm || 0.73x
 
|}
 
|}
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== Compiler support ==
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{{empty section}}
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== Architecture ==
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{{empty section}}
  
 
== Die Shot ==
 
== Die Shot ==
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[[File:p6 tualatin die slide.png|thumb|right|200px|Tualatin]]
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=== {{intel|Klamath|l=core}} ===
 
* [[280 nm process]] [[CMOS]]
 
* [[280 nm process]] [[CMOS]]
 
* 4 metal layers
 
* 4 metal layers
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*  540-pin BGA (Ball Grid Array)
 
*  540-pin BGA (Ball Grid Array)
 
[[File:intel p6 die shot.png]]
 
[[File:intel p6 die shot.png]]
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=== Pentium Pro ===
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* [[0.35 µm process]]
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* 5,500,000 transistors
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[[File:pentium pro die shot.png|700px]]
  
 
== References ==
 
== References ==
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* Brand, Adam, et al. "Intel’s 0.25 micron, 2.0 volts logic process technology." Intel Technology Journal Q 3 (1998): 1998.
 
* Brand, Adam, et al. "Intel’s 0.25 micron, 2.0 volts logic process technology." Intel Technology Journal Q 3 (1998): 1998.
 
* Integrated Circuit Engineering (ICE) Corporation. "Construction Analysis Intel 266MHz 32-Bit Pentium II (Klamath) Processor"; Shared Construction Analysis (SCA) 9706-542.
 
* Integrated Circuit Engineering (ICE) Corporation. "Construction Analysis Intel 266MHz 32-Bit Pentium II (Klamath) Processor"; Shared Construction Analysis (SCA) 9706-542.
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== Documents ==
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* [[:File:24281603.pdf|Intel Architecture Optimization Manual]], Document 242816-003; 1997

Latest revision as of 20:34, 22 February 2020

Edit Values
P6 µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionOctober, 1995
Phase-outDecember, 2000
Process350 nm, 250 nm
Instructions
ISAx86-32
Succession
Pentium Pro processor with 1M of L2 cache.

P6 was the microarchitecture for Intel's for desktops and servers as a successor to P5. Introduced in 1995 and continued until 2000, P6 was fabricated using 350 nm and 250 nm processes. P6 was made obsolete by NetBurst in late 2000.

Codenames[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Process Technology[edit]

P6 was manufactured on the 0.35 µm process initially and later enjoyed a process shrink down to 0.25 µm, allowing for considerably lower voltage and higher clock speed at a smaller silicon die area. The shrink introduced a 5th metal layer which further reduced RC delay and die area. Intel claimed the channel area was reduced by 50% with the introduction of the 5th layer. The 5th layer also enabled Intel to support C4 packaging.

0.35 µm 0.25 µm Δ
Contacted Gate Pitch​ 550 nm 500 nm 0.91x
Interconnect Pitch 880 nm 640 nm 0.73x

Compiler support[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Architecture[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Die Shot[edit]

Tualatin

Klamath[edit]

  • 280 nm process CMOS
  • 4 metal layers
  • 7,500,000 transistors
  • 13.3 mm x 14.6 mm
  • 194.8 mm² die size
  • 540-pin BGA (Ball Grid Array)

intel p6 die shot.png

Pentium Pro[edit]

pentium pro die shot.png

References[edit]

  • Schutz, J., and R. Wallace. "A 450 MHz IA32 P6 family microprocessor." Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International. IEEE, 1998.
  • Brand, Adam, et al. "Intel’s 0.25 micron, 2.0 volts logic process technology." Intel Technology Journal Q 3 (1998): 1998.
  • Integrated Circuit Engineering (ICE) Corporation. "Construction Analysis Intel 266MHz 32-Bit Pentium II (Klamath) Processor"; Shared Construction Analysis (SCA) 9706-542.

Documents[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/p6&oldid=96113"
Facts about "P6 - Microarchitectures - Intel"
RDF feed
codenameP6 +
designerIntel +
first launchedOctober 1995 +
full page nameintel/microarchitectures/p6 +
instance ofmicroarchitecture +
instruction set architecturex86-32 +
manufacturerIntel +
microarchitecture typeCPU +
nameP6 +
phase-outDecember 2000 +
process350 nm (0.35 μm, 3.5e-4 mm) + and 250 nm (0.25 μm, 2.5e-4 mm) +