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{{intel title|Xeon D-1559}}
 
{{intel title|Xeon D-1559}}
−
{{mpu
+
{{chip
−
| name               = Intel Xeon D-1559
+
|name=Xeon D-1559
−
| image               =  
+
|image=broadwell de (front).png
−
| image size          =
+
|back image=broadwell de (back).png
−
| no image            = Yes
+
|designer=Intel
−
| caption            =  
+
|manufacturer=Intel
−
| designer           = Intel
+
|model number=D-1559
−
| manufacturer       = Intel
+
|part number=GG8067402570801
−
| model number       = D-1559
+
|s-spec=SR2M5
−
| part number         = GG8067402570801
+
|market=Server
−
| market             = Server
+
|market 2=Embedded
−
| market 2           = Embedded
+
|first announced=April, 2016
−
| first announced     =  
+
|first launched=April, 2016
−
| first launched     = April, 2016
+
|release price (tray)=$727.00
−
| last order          =  
+
|family=Xeon D
−
| last shipment      =  
+
|series=D-1500
 +
|locked=Yes
 +
|frequency=1,500 MHz
 +
|turbo frequency1=2,100 MHz
 +
|bus type=DMI 2.0
 +
|clock multiplier=15
 +
|isa=x86-64
 +
|isa family=x86
 +
|microarch=Broadwell
 +
|platform=Grangeville
 +
|core name=Broadwell DE
 +
|core family=6
 +
|core model=6
 +
|core stepping=Y0
 +
|process=14 nm
 +
|transistors=4,700,000,000
 +
|technology=CMOS
 +
|die area=306.18 mm²
 +
|word size=64 bit
 +
|core count=12
 +
|thread count=24
 +
|max cpus=1
 +
|max memory=128 GiB
 +
|tdp=45 W
 +
|temp min=-40 °C
 +
|temp max=85 °C
 +
|package name 1=intel,fcbga_1667
 +
}}
 +
'''Xeon D-1559''' is a {{arch|64}} [[dodeca-core]] [[x86]] microserver SoC introduced by [[Intel]] in mid [[2016]]. The D-1559 is based on the {{intel|Broadwell|l=arch}} microarchitecture and is fabricated on their [[14 nm process]]. It operates at 1.5 GHz with a TDP of 45 W and a {{intel|turbo boost|turbo frequency}} of 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.
  
−
| family              = Xeon D
 
−
| series              = D-1500
 
−
| locked              = Yes
 
−
| frequency          = 1500 MHz
 
−
| turbo frequency    = Yes
 
−
| turbo frequency1    = 2100 MHz
 
−
| turbo frequency2    =
 
−
| turbo frequency3    =
 
−
| turbo frequency4    =
 
−
| bus type            = DMI 2.0
 
−
| bus speed          =
 
−
| clock multiplier    = 15
 
−
| s-spec              = SR2M5
 
−
| s-spec qs          =
 
−
| s-spec es          =
 
−
| cpuid              =
 
−
 
−
| isa family          = x86
 
−
| isa                = x86-64
 
−
| microarch          = Broadwell
 
−
| platform            = Grangeville
 
−
| core name          = Broadwell DE
 
−
| core stepping      = Y0
 
−
| process            = 14 nm
 
−
| transistors        =
 
−
| technology          = CMOS
 
−
| die size            =
 
−
| word size          = 64 bit
 
−
| core count          = 12
 
−
| thread count        = 24
 
−
| max cpus            = 1
 
−
| max memory          = 128 GB
 
−
 
−
| electrical          = Yes
 
−
| sdp                =
 
−
| tdp                = 45 W
 
−
| ctdp down          =
 
−
| ctdp down frequency =
 
−
| ctdp up            =
 
−
| temp max            = 85 °C
 
−
| temp min            = -40 °C
 
−
 
−
| packaging          = Yes
 
−
| package            = FCBGA1667
 
−
| package type        = FCBGA
 
−
| package pitch      = 0.7 mm
 
−
| package size        = 37.5 mm x 37.5 mm x 3.557 mm
 
−
| socket              = BGA1667
 
−
| socket type        = BGA
 
−
}}
 
−
The '''{{intel|Xeon D}}-1559''' is a {{arch|64}} octa-core [[x86-64]] microserver SoC that was introduced by [[Intel]] in April of 2016. The D-1559 operates at 1.5 GHz with a turbo frequency of 2.1 GHz. This chip, which is based on the [[intel/microarchitectures/broadwell|Broadwell]] [[microarchitecture]] and manufactured in [[14 nm process]], has a TDP of 45 W and can support up to 128 GB of RAM (DDR3L/DDR4).
 
  
 
== Cache ==
 
== Cache ==
−
{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
+
{{main|intel/microarchitectures/broadwell (server)#Memory_Hierarchy|l1=Broadwell § Cache}}
−
{{cache info
+
{{cache size
 +
|l1 cache=768 KiB
 
|l1i cache=384 KiB
 
|l1i cache=384 KiB
 
|l1i break=12x32 KiB
 
|l1i break=12x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
−
|l1i extra=(per core)
 
 
|l1d cache=384 KiB
 
|l1d cache=384 KiB
 
|l1d break=12x32 KiB
 
|l1d break=12x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
−
|l1d extra=(per core)
+
|l1d policy=write-back
 
|l2 cache=3 MiB
 
|l2 cache=3 MiB
 
|l2 break=12x256 KiB
 
|l2 break=12x256 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
−
|l2 extra=(per core)
+
|l2 policy=write-back
 
|l3 cache=18 MiB
 
|l3 cache=18 MiB
 
|l3 break=12x1.5 MiB
 
|l3 break=12x1.5 MiB
−
|l3 extra=(per core)
+
|l3 desc=16-way set associative
 +
|l3 policy=write-back
 
}}
 
}}
  
Line 93: Line 71:
  
 
== Memory controller ==
 
== Memory controller ==
−
{{integrated memory controller
+
{{memory controller
−
| type               = DDR3L-1333
+
|type=DDR4-2133
−
| type 2            = DDR3L-1600
+
|ecc=Yes
−
| type 3            = DDR4-1600
+
|max mem=128 GiB
−
| type 4            = DDR4-1867
+
|controllers=1
−
| type 5            = DDR4-2133
+
|channels=2
−
| controllers       = 1
+
|max bandwidth=31.78 GiB/s
−
| channels           = 2
+
|bandwidth schan=15.89 GiB/s
−
| ecc support        = Yes
+
|bandwidth dchan=31.78 GiB/s
−
| max bandwidth     =  
 
−
| bandwidth schan   =  
 
−
| bandwidth dchan   =
 
−
| max memory        = 128 GB
 
 
}}
 
}}
  
 
== Expansions ==
 
== Expansions ==
−
{{mpu expansions
+
{{expansions main
−
| pcie revision      = 2.0
+
|
−
| pcie revision 2    = 3.0
+
{{expansions entry
−
| pcie lanes         = 8
+
|type=PCIe
−
| pcie lanes 2       = 32
+
|pcie revision=3.0
−
| pcie config       = x4
+
|pcie lanes=24
−
| pcie config 1      = x8
+
|pcie config=x16
−
| pcie config 2     = x16
+
|pcie config 2=x8
−
| usb revision       = 2.0
+
|pcie config 3=x4
−
| usb revision 2     = 3.0
+
}}
−
| usb ports         = 8
+
{{expansions entry
−
| sata ports        = 6
+
|type=PCIe
−
| integrated lan    = Yes
+
|pcie revision=2.0
−
| uart              = Yes
+
|pcie lanes=8
−
| gp io              = Yes
+
|pcie config=x8
 +
|pcie config 2=x4
 +
}}
 +
{{expansions entry
 +
|type=USB
 +
|usb revision=3.0
 +
|usb ports=4
 +
}}
 +
{{expansions entry
 +
|type=USB
 +
|usb revision=2.0
 +
|usb ports=4
 +
}}
 +
{{expansions entry
 +
|type=SATA
 +
|sata revision=3
 +
|sata ports=6
 +
}}
 
}}
 
}}
  
 
== Networking ==
 
== Networking ==
−
{{soc networking
+
{{network
−
| SFI interface    = Yes
+
|eth opts=Yes
−
| KR interface      = Yes
+
|10ge=Yes
−
| KR4 interface    = No
+
|10ge ports=2
−
| KX interface      = Yes
 
−
| KX4 interface    = No
 
−
| 10Base-T          = No
 
−
| 100Base-T        = No
 
−
| 1000Base-T        = Yes
 
−
| 10GBase-T        = Yes
 
 
}}
 
}}
  
 
== Features ==
 
== Features ==
−
{{mpu features
+
{{x86 features
−
| em64t      = Yes
+
|real=Yes
−
| nx          = Yes
+
|protected=Yes
−
| txt        = Yes
+
|smm=Yes
−
| tsx        = Yes
+
|fpu=Yes
−
| ht          = Yes
+
|x8616=Yes
−
| tbt2        = Yes
+
|x8632=Yes
−
| bpt        =  
+
|x8664=Yes
−
| vt-x        = Yes
+
|nx=Yes
−
| vt-d        = Yes
+
|mmx=Yes
−
| mmx        = Yes
+
|emmx=Yes
−
| sse         = Yes
+
|sse=Yes
−
| sse2       = Yes
+
|sse2=Yes
−
| sse3       = Yes
+
|sse3=Yes
−
| ssse3       = Yes
+
|ssse3=Yes
−
| sse4        = Yes
+
|sse41=Yes
−
| sse4.1      = Yes
+
|sse42=Yes
−
| sse4.2      = Yes
+
|sse4a=No
−
| aes         = Yes
+
|avx=Yes
−
| avx        = Yes
+
|avx2=Yes
−
| avx2        = Yes
+
|avx512f=No
−
| bmi        = Yes
+
|avx512cd=No
−
| bmi1        = Yes
+
|avx512er=No
−
| bmi2        = Yes
+
|avx512pf=No
−
| f16c        = Yes
+
|avx512bw=No
−
| fma3        = Yes
+
|avx512dq=No
−
| sgx         =  
+
|avx512vl=No
−
| eist        = Yes
+
|avx512ifma=No
−
| secure key = Yes
+
|avx512vbmi=No
−
| os guard   = Yes
+
|avx5124fmaps=No
 +
|avx512vnni=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=Yes
 +
|osguard=Yes
 +
|intqat=No
 +
|dlboost=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
|em64t=Yes
 +
|vt-x=Yes
 +
|vt-d=Yes
 +
|sse4=Yes
 +
|sse4_1=Yes
 +
|sse4_2=Yes
 +
|bmi=Yes
 +
|secure key=Yes
 +
|os guard=Yes
 
}}
 
}}

Latest revision as of 01:16, 1 April 2019

Edit Values
Xeon D-1559
broadwell de (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberD-1559
Part NumberGG8067402570801
S-SpecSR2M5
MarketServer, Embedded
IntroductionApril, 2016 (announced)
April, 2016 (launched)
Release Price$727.00 (tray)
ShopAmazon
General Specs
FamilyXeon D
SeriesD-1500
LockedYes
Frequency1,500 MHz
Turbo Frequency2,100 MHz (1 core)
Bus typeDMI 2.0
Clock multiplier15
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureBroadwell
PlatformGrangeville
Core NameBroadwell DE
Core Family6
Core Model6
Core SteppingY0
Process14 nm
Transistors4,700,000,000
TechnologyCMOS
Die306.18 mm²
Word Size64 bit
Cores12
Threads24
Max Memory128 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP45 W
OP Temperature-40 °C – 85 °C
Packaging
PackageFCBGA-1667 (FCBGA)
Dimension37.5 mm × 37.5 mm × 3.557 mm
Pitch0.7 mm
Contacts1667
broadwell de (back).png

Xeon D-1559 is a 64-bit dodeca-core x86 microserver SoC introduced by Intel in mid 2016. The D-1559 is based on the Broadwell microarchitecture and is fabricated on their 14 nm process. It operates at 1.5 GHz with a TDP of 45 W and a turbo frequency of 2.1 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2133 memory.


Cache[edit]

Main article: Broadwell § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associative 
L1D$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back
L2$3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
  12x256 KiB8-way set associativewrite-back
L3$18 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
  12x1.5 MiB16-way set associativewrite-back

Graphics[edit]

This SoC has no integrated graphics processing unit.

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Max Mem128 GiB
Controllers1
Channels2
Max Bandwidth31.78 GiB/s
32,542.72 MiB/s
34.124 GB/s
34,123.515 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.78 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 24
Configuration: x16, x8, x4
PCIeRevision: 2.0
Max Lanes: 8
Configuration: x8, x4
USBRevision: 3.0
Max Ports: 4
USBRevision: 2.0
Max Ports: 4
SATARevision: 3
Max Ports: 6


Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
Ethernet
10GbEYes (Ports: 2)

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
TXTTrusted Execution Technology (SMX)
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_d/d-1559&oldid=87690"
Facts about "Xeon D-1559 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description8-way set associative +
l2$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
l3$ size18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) +