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Difference between revisions of "cavium/octeon/cn3630-500bg1521-nsp"
< cavium‎ | octeon

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{{cavium title|CN3630-500 NSP}}
 
{{cavium title|CN3630-500 NSP}}
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{{mpu
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{{chip
 
| name                = Cavium CN3630-500 NSP
 
| name                = Cavium CN3630-500 NSP
 
| no image            =  
 
| no image            =  
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| model number        = CN3630-500 NSP
 
| model number        = CN3630-500 NSP
 
| part number        = CN3630-500BG1521-NSP
 
| part number        = CN3630-500BG1521-NSP
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| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
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| part number 4      =
 
| market              = Networking
 
| market              = Networking
 
| first announced    = August, 2005
 
| first announced    = August, 2005
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| max memory addr    =  
 
| max memory addr    =  
  
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| electrical          = Yes
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| electrical          =  
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| power              = 22 W
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| power              =  
 
| v core              =  
 
| v core              =  
 
| v core tolerance    =  
 
| v core tolerance    =  
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| tambient max        =  
 
| tambient max        =  
  
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| packaging          = Yes
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|package module 1={{packages/cavium/fcbga-1521}}
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| package 0          = BGA-1521
 
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| package 0 type      = BGA
 
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| package 0 pins      = 1521
 
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| package 0 pitch    =
 
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| package 0 width    =
 
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| package 0 length    =
 
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| socket 0            =
 
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| socket 0 type      =
 
 
}}
 
}}
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The '''CN3630-500 NSP''' is a {{arch|64}} [[quad-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
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== Cache ==
 +
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
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{{cache size
 +
|l1 cache=160 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
 +
|l1i desc=64-way set associative
 +
|l1d cache=32 KiB
 +
|l1d break=4x8 KiB
 +
|l1d desc=64-way set associative
 +
|l1d policy=Write-through
 +
|l2 cache=512 KiB
 +
|l2 break=1x512 KiB
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|l2 desc=8-way set associative
 +
}}
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 +
== Memory controller ==
 +
{{memory controller
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|type=DDR2-800
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|ecc=Yes
 +
|max mem=16 GiB
 +
|controllers=1
 +
|channels=1
 +
|width=64 bit
 +
|max bandwidth=5.96 GiB/s
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|bandwidth schan=5.96 GiB/s
 +
}}
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== Expansions ==
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{{expansions
 +
|pcix width=64 bit
 +
|pcix clock=133.33 MHz
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|pcix rate=1,017.25 MiB/s
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|pcix extra=host or slave
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|uart=yes
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|uart ports=2
 +
|gp io=Yes
 +
}}
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== Networking ==
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{{network
 +
|mii opts=Yes
 +
|rgmii=yes
 +
|rgmii ports=8
 +
|spi opts=Yes
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|spi42=Yes
 +
|spi42 ports=2
 +
}}
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 +
== Hardware Accelerators ==
 +
{{accelerators
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|encryption=Yes
 +
|encryption type=DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
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|regex=Yes
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|regex feature=16 Engines
 +
|compression=Yes
 +
|decompression=Yes
 +
|tcp=Yes
 +
|qos=Yes
 +
}}
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 +
== Block diagram ==
 +
[[File:octeon cn38xx block diagram.png|750px]]
 +
 +
== Datasheet ==
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* [[:File:octeon cn38xx and cn36xx product brief.pdf|OCTEON CN38XX /CN36XX 4 to 16-Core Product Brief]]

Latest revision as of 15:11, 13 December 2017

Edit Values
Cavium CN3630-500 NSP
octeon cn38xx.png
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN3630-500 NSP
Part NumberCN3630-500BG1521-NSP
MarketNetworking
IntroductionAugust, 2005 (announced)
August, 2005 (launched)
General Specs
FamilyOCTEON
SeriesCN3600
Frequency500 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Core NamecnMIPS
Process130 nm
TechnologyCMOS
Word Size64 bit
Cores4
Threads4
Max Memory16 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Packaging
PackageFCBGA-1521 (BGA)
Ball Count1521
InterconnectBGA-1521

The CN3630-500 NSP is a 64-bit quad-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2005. This processor, which incorporates four cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$160 KiB
163,840 B
0.156 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB64-way set associative 
L1D$32 KiB
32,768 B
0.0313 MiB
4x8 KiB64-way set associativeWrite-through
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB8-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Max Mem16 GiB
Controllers1
Channels1
Width64 bit
Max Bandwidth5.96 GiB/s
6,103.04 MiB/s
6.4 GB/s
6,399.501 MB/s
0.00582 TiB/s
0.0064 TB/s
Bandwidth
Single 5.96 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width64 bit
Clock133.33 MHz
Rate1,017.25 MiB/s
Featureshost or slave
UART
Ports2
GP I/OYes


Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes (Ports: 8)
SPI
SPI-4.2Yes (Ports: 2)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Encryption
Hardware ImplementationYes
TypesDES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
RegEx
RegExYes
Features16 Engines
Networking
TCPYes
QoSYes
Compression
CompressionYes
DecompressionYes

Block diagram[edit]

octeon cn38xx block diagram.png

Datasheet[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3630-500bg1521-nsp&oldid=70210"
Facts about "CN3630-500 NSP - Cavium"
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CN3630-500 NSP - Cavium#package +
base frequency500 MHz (0.5 GHz, 500,000 kHz) +
core count4 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedAugust 2005 +
first launchedAugust 2005 +
full page namecavium/octeon/cn3630-500bg1521-nsp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size160 KiB (163,840 B, 0.156 MiB) +
l1d$ description64-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description64-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldateAugust 2005 +
main imageFile:octeon cn38xx.png +
manufacturerTSMC +
market segmentNetworking +
max cpu count1 +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3630-500 NSP +
nameCavium CN3630-500 NSP +
packageFCBGA-1521 +
part numberCN3630-500BG1521-NSP +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3600 +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count4 +
word size64 bit (8 octets, 16 nibbles) +