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{{cavium title|CN3630-400 NSP}} | {{cavium title|CN3630-400 NSP}} | ||
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| name = Cavium CN3630-400 NSP | | name = Cavium CN3630-400 NSP | ||
| no image = | | no image = | ||
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| model number = CN3630-400 NSP | | model number = CN3630-400 NSP | ||
| part number = CN3630-400BG1521-NSP | | part number = CN3630-400BG1521-NSP | ||
− | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Networking | | market = Networking | ||
| first announced = August, 2005 | | first announced = August, 2005 | ||
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| max memory addr = | | max memory addr = | ||
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| power = 14 W | | power = 14 W | ||
| v core = | | v core = | ||
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| tambient max = | | tambient max = | ||
− | | | + | |package module 1={{packages/cavium/fcbga-1521}} |
− | | | + | }} |
− | | | + | The '''CN3630-400 NSP''' is a {{arch|64}} [[quad-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 400 MHz and dissipates 14 Watts. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory. |
− | | | + | |
− | | | + | == Cache == |
− | | | + | {{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}} |
− | | | + | {{cache size |
− | | | + | |l1 cache=160 KiB |
− | | | + | |l1i cache=128 KiB |
− | | | + | |l1i break=4x32 KiB |
+ | |l1i desc=64-way set associative | ||
+ | |l1d cache=32 KiB | ||
+ | |l1d break=4x8 KiB | ||
+ | |l1d desc=64-way set associative | ||
+ | |l1d policy=Write-through | ||
+ | |l2 cache=512 KiB | ||
+ | |l2 break=1x512 KiB | ||
+ | |l2 desc=8-way set associative | ||
}} | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR2-800 | ||
+ | |ecc=Yes | ||
+ | |max mem=16 GiB | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=64 bit | ||
+ | |max bandwidth=5.96 GiB/s | ||
+ | |bandwidth schan=5.96 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | |pcix width=64 bit | ||
+ | |pcix clock=133.33 MHz | ||
+ | |pcix rate=1,017.25 MiB/s | ||
+ | |pcix extra=host or slave | ||
+ | |uart=yes | ||
+ | |uart ports=2 | ||
+ | |gp io=Yes | ||
+ | }} | ||
+ | |||
+ | == Networking == | ||
+ | {{network | ||
+ | |mii opts=Yes | ||
+ | |rgmii=yes | ||
+ | |rgmii ports=8 | ||
+ | |spi opts=Yes | ||
+ | |spi42=Yes | ||
+ | |spi42 ports=2 | ||
+ | }} | ||
+ | |||
+ | == Hardware Accelerators == | ||
+ | {{accelerators | ||
+ | |encryption=Yes | ||
+ | |encryption type=DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH | ||
+ | |regex=Yes | ||
+ | |regex feature=16 Engines | ||
+ | |compression=Yes | ||
+ | |decompression=Yes | ||
+ | |tcp=Yes | ||
+ | |qos=Yes | ||
+ | }} | ||
+ | |||
+ | == Block diagram == | ||
+ | [[File:octeon cn38xx block diagram.png|750px]] | ||
+ | |||
+ | == Datasheet == | ||
+ | * [[:File:octeon cn38xx and cn36xx product brief.pdf|OCTEON CN38XX /CN36XX 4 to 16-Core Product Brief]] |
Latest revision as of 16:11, 13 December 2017
Edit Values | |||||||
Cavium CN3630-400 NSP | |||||||
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General Info | |||||||
Designer | Cavium | ||||||
Manufacturer | TSMC | ||||||
Model Number | CN3630-400 NSP | ||||||
Part Number | CN3630-400BG1521-NSP | ||||||
Market | Networking | ||||||
Introduction | August, 2005 (announced) August, 2005 (launched) | ||||||
General Specs | |||||||
Family | OCTEON | ||||||
Series | CN3600 | ||||||
Frequency | 400 MHz | ||||||
Microarchitecture | |||||||
ISA | MIPS64 (MIPS) | ||||||
Microarchitecture | cnMIPS | ||||||
Core Name | cnMIPS | ||||||
Process | 130 nm | ||||||
Technology | CMOS | ||||||
Word Size | 64 bit | ||||||
Cores | 4 | ||||||
Threads | 4 | ||||||
Max Memory | 16 GiB | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Electrical | |||||||
Power dissipation | 14 W | ||||||
Packaging | |||||||
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The CN3630-400 NSP is a 64-bit quad-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2005. This processor, which incorporates four cnMIPS cores, operates at 400 MHz and dissipates 14 Watts. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Networking[edit]
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Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN3630-400 NSP - Cavium"