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Difference between revisions of "cavium/octeon/cn3005-500bg350-cp"
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{{cavium title|CN3005-500 CP}} | {{cavium title|CN3005-500 CP}} | ||
− | {{ | + | {{chip |
| name = Cavium CN3005-500 CP | | name = Cavium CN3005-500 CP | ||
− | | no image = cn3005-15.png | + | | no image = |
− | + | | image = cn3005-15.png | |
| image size = | | image size = | ||
| caption = | | caption = | ||
| designer = Cavium | | designer = Cavium | ||
| manufacturer = TSMC | | manufacturer = TSMC | ||
− | | model number = CN3005 | + | | model number = CN3005-500 CP |
| part number = CN3005-500BG350-CP | | part number = CN3005-500BG350-CP | ||
− | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Embedded | | market = Embedded | ||
| first announced = January 30, 2006 | | first announced = January 30, 2006 | ||
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| last order = | | last order = | ||
| last shipment = | | last shipment = | ||
− | | release price = | + | | release price = |
| family = OCTEON | | family = OCTEON | ||
Line 52: | Line 52: | ||
| max memory addr = | | max memory addr = | ||
− | + | ||
| power = 4 W | | power = 4 W | ||
| v core = | | v core = | ||
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| socket 0 type = | | socket 0 type = | ||
}} | }} | ||
− | The '''CN3005-500 CP''' is a {{arch|64}} [[single-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]] and introduced in [[ | + | The '''CN3005-500 CP''' is a {{arch|64}} [[single-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 memory. |
== Cache == | == Cache == | ||
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|l2 desc=2-way set associative | |l2 desc=2-way set associative | ||
}} | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR2-533 | ||
+ | |ecc=No | ||
+ | |max mem=2 GiB | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=16 bit | ||
+ | |max bandwidth=1,017 MiB/s | ||
+ | |bandwidth schan=1,017 MiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | |pci width=32 bit | ||
+ | |pci clock=66.66 MHz | ||
+ | |pci rate=254.31 MiB/s | ||
+ | |pci extra=host or slave | ||
+ | |usb revision=2.0 | ||
+ | |usb ports=1 | ||
+ | |usb rate=60 MB/s | ||
+ | |usb extra=host / PHY | ||
+ | |uart=yes | ||
+ | |uart ports=2 | ||
+ | |gp io=Yes | ||
+ | }} | ||
+ | |||
+ | == Networking == | ||
+ | {{network | ||
+ | |mii opts=Yes | ||
+ | |rgmii=yes | ||
+ | |rgmii ports=1 | ||
+ | |gmii=yes | ||
+ | |gmii ports=1 | ||
+ | }} | ||
+ | |||
+ | == Hardware Accelerators == | ||
+ | {{accelerators | ||
+ | |tcp=Yes | ||
+ | |qos=Yes | ||
+ | }} | ||
+ | |||
+ | == Block diagram == | ||
+ | [[File:cn3005 block diagram.png|750px]] | ||
+ | |||
+ | == Datasheet == | ||
+ | * [[:File:octeon cn30xx product brief.pdf|OCTEON CN30XX Processors Product Brief]] |
Latest revision as of 16:10, 13 December 2017
Edit Values | |
Cavium CN3005-500 CP | |
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General Info | |
Designer | Cavium |
Manufacturer | TSMC |
Model Number | CN3005-500 CP |
Part Number | CN3005-500BG350-CP |
Market | Embedded |
Introduction | January 30, 2006 (announced) May 1, 2006 (launched) |
General Specs | |
Family | OCTEON |
Series | CN3000 |
Frequency | 500 MHz |
Microarchitecture | |
ISA | MIPS64 (MIPS) |
Microarchitecture | cnMIPS |
Core Name | cnMIPS |
Process | 130 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 1 |
Threads | 1 |
Max Memory | 2 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Power dissipation | 4 W |
The CN3005-500 CP is a 64-bit single-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2006. This processor, which incorporates a single cnMIPS core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 memory.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Networking[edit]
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Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN3005-500 CP - Cavium"
base frequency | 500 MHz (0.5 GHz, 500,000 kHz) + |
core count | 1 + |
core name | cnMIPS + |
designer | Cavium + |
family | OCTEON + |
first announced | January 30, 2006 + |
first launched | May 1, 2006 + |
full page name | cavium/octeon/cn3005-500bg350-cp + |
has ecc memory support | false + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
instance of | microprocessor + |
isa | MIPS64 + |
isa family | MIPS + |
l1$ size | 24 KiB (24,576 B, 0.0234 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l2$ description | 2-way set associative + |
l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |
ldate | May 1, 2006 + |
main image | ![]() |
manufacturer | TSMC + |
market segment | Embedded + |
max cpu count | 1 + |
max memory | 2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) + |
max memory bandwidth | 0.993 GiB/s (1,017 MiB/s, 1.066 GB/s, 1,066.402 MB/s, 9.698868e-4 TiB/s, 0.00107 TB/s) + |
max memory channels | 1 + |
microarchitecture | cnMIPS + |
model number | CN3005-500 CP + |
name | Cavium CN3005-500 CP + |
part number | CN3005-500BG350-CP + |
power dissipation | 4 W (4,000 mW, 0.00536 hp, 0.004 kW) + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
series | CN3000 + |
smp max ways | 1 + |
supported memory type | DDR2-533 + |
technology | CMOS + |
thread count | 1 + |
word size | 64 bit (8 octets, 16 nibbles) + |