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{{cavium title|CN3005-300 SCP}}
 
{{cavium title|CN3005-300 SCP}}
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{{mpu
+
{{chip
 
| name                = Cavium CN3005-300 SCP
 
| name                = Cavium CN3005-300 SCP
−
| no image            = cn3005-15.png
+
| no image            =
−
| image              =
+
| image              = cn3005-15.png
 
| image size          =  
 
| image size          =  
 
| caption            =  
 
| caption            =  
 
| designer            = Cavium
 
| designer            = Cavium
 
| manufacturer        = TSMC
 
| manufacturer        = TSMC
−
| model number        = CN3005
+
| model number        = CN3005-300 SCP
 
| part number        = CN3005-300BG350-SCP
 
| part number        = CN3005-300BG350-SCP
−
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Embedded
 
| market              = Embedded
 
| first announced    = January 30, 2006  
 
| first announced    = January 30, 2006  
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| last order          =  
 
| last order          =  
 
| last shipment      =  
 
| last shipment      =  
−
| release price      =  
+
| release price      = $19
  
 
| family              = OCTEON
 
| family              = OCTEON
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| die width          =  
 
| die width          =  
 
| die length          =  
 
| die length          =  
−
| word size          =  
+
| word size          = 64 bit
−
| core count          =  
+
| core count          = 1
−
| thread count        =  
+
| thread count        = 1
−
| max cpus            =  
+
| max cpus            = 1
 
| max memory          = 2 GiB
 
| max memory          = 2 GiB
 
| max memory addr    =  
 
| max memory addr    =  
  
−
| electrical          = Yes
+
 
 
| power              = 2 W
 
| power              = 2 W
 
| v core              =  
 
| v core              =  
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| socket 0 type      =  
 
| socket 0 type      =  
 
}}
 
}}
−
The '''CN3005-300 SCP''' is a {{arch|64}} [[single-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in early [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 300 MHz and dissipates 2 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration.
+
The '''CN3005-300 SCP''' is a {{arch|64}} [[single-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in early [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 300 MHz and dissipates 2 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 memory.
 +
 
 +
== Cache ==
 +
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
 +
{{cache size
 +
|l1 cache=24 KiB
 +
|l1i cache=16 KiB
 +
|l1i break=1x16 KiB
 +
|l1i desc=2-way set associative
 +
|l1d cache=8 KiB
 +
|l1d break=1x8 KiB
 +
|l1d desc=64-way set associative
 +
|l1d policy=Write-through
 +
|l2 cache=64 KiB
 +
|l2 break=1x64 KiB
 +
|l2 desc=2-way set associative
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR2-533
 +
|ecc=No
 +
|max mem=2 GiB
 +
|controllers=1
 +
|channels=1
 +
|width=16 bit
 +
|max bandwidth=1,017 MiB/s
 +
|bandwidth schan=1,017 MiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions
 +
|pci width=32 bit
 +
|pci clock=66.66 MHz
 +
|pci rate=254.31 MiB/s
 +
|pci extra=host or slave
 +
|usb revision=2.0
 +
|usb ports=1
 +
|usb rate=60 MB/s
 +
|usb extra=host / PHY
 +
|uart=yes
 +
|uart ports=2
 +
|gp io=Yes
 +
}}
 +
 
 +
== Networking ==
 +
{{network
 +
|mii opts=Yes
 +
|rgmii=yes
 +
|rgmii ports=1
 +
|gmii=yes
 +
|gmii ports=1
 +
}}
 +
 
 +
== Hardware Accelerators ==
 +
{{accelerators
 +
|encryption=Yes
 +
|encryption type=DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
 +
|tcp=Yes
 +
|qos=Yes
 +
}}
 +
 
 +
== Block diagram ==
 +
[[File:cn3005 block diagram.png|750px]]
 +
 
 +
== Datasheet ==
 +
* [[:File:octeon cn30xx product brief.pdf|OCTEON CN30XX Processors Product Brief]]

Latest revision as of 15:10, 13 December 2017

Edit Values
Cavium CN3005-300 SCP
cn3005-15.png
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN3005-300 SCP
Part NumberCN3005-300BG350-SCP
MarketEmbedded
IntroductionJanuary 30, 2006 (announced)
May 1, 2006 (launched)
Release Price$19
General Specs
FamilyOCTEON
SeriesCN3000
Frequency300 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Core NamecnMIPS
Process130 nm
TechnologyCMOS
Word Size64 bit
Cores1
Threads1
Max Memory2 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation2 W

The CN3005-300 SCP is a 64-bit single-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in early 2006. This processor, which incorporates a single cnMIPS core, operates at 300 MHz and dissipates 2 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 memory.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$24 KiB
24,576 B
0.0234 MiB
L1I$16 KiB
16,384 B
0.0156 MiB
1x16 KiB2-way set associative 
L1D$8 KiB
8,192 B
0.00781 MiB
1x8 KiB64-way set associativeWrite-through
L2$64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
  1x64 KiB2-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-533
Supports ECCNo
Max Mem2 GiB
Controllers1
Channels1
Width16 bit
Max Bandwidth1,017 MiB/s
0.993 GiB/s
1.066 GB/s
1,066.402 MB/s
9.698868e-4 TiB/s
0.00107 TB/s
Bandwidth
Single 1,017 MiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI
Width32 bit
Clock66.66 MHz
Rate254.31 MiB/s
Featureshost or slave
USB
Revision2.0
Ports1
Rate60 MB/s
Featureshost / PHY
UART
Ports2
GP I/OYes


Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
GMIIYes (Ports: 1)
RGMIIYes (Ports: 1)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Encryption
Hardware ImplementationYes
TypesDES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
Networking
TCPYes
QoSYes

Block diagram[edit]

cn3005 block diagram.png

Datasheet[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3005-300bg350-scp&oldid=70163"
Facts about "CN3005-300 SCP - Cavium"
RDF feed
base frequency300 MHz (0.3 GHz, 300,000 kHz) +
core count1 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedJanuary 30, 2006 +
first launchedMay 1, 2006 +
full page namecavium/octeon/cn3005-300bg350-scp +
has ecc memory supportfalse +
has hardware accelerators for cryptographytrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size24 KiB (24,576 B, 0.0234 MiB) +
l1d$ description64-way set associative +
l1d$ size8 KiB (8,192 B, 0.00781 MiB) +
l1i$ description2-way set associative +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
l2$ description2-way set associative +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
ldateMay 1, 2006 +
main imageFile:cn3005-15.png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory bandwidth0.993 GiB/s (1,017 MiB/s, 1.066 GB/s, 1,066.402 MB/s, 9.698868e-4 TiB/s, 0.00107 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3005-300 SCP +
nameCavium CN3005-300 SCP +
part numberCN3005-300BG350-SCP +
power dissipation2 W (2,000 mW, 0.00268 hp, 0.002 kW) +
process130 nm (0.13 μm, 1.3e-4 mm) +
release price$ 19.00 (€ 17.10, £ 15.39, ¥ 1,963.27) +
seriesCN3000 +
smp max ways1 +
supported memory typeDDR2-533 +
technologyCMOS +
thread count1 +
word size64 bit (8 octets, 16 nibbles) +