From WikiChip
Difference between revisions of "socionext/sc2a11"
< socionext

(its ECC not EEC)
 
(17 intermediate revisions by 4 users not shown)
Line 1: Line 1:
 
{{socionext title|SC2A11}}
 
{{socionext title|SC2A11}}
−
{{mpu
+
{{chip
−
| future             = Yes
+
|future=Yes
−
| name               = Socionext SC2A11
+
|name=Socionext SC2A11
−
| no image           = Yes
+
|image=SC2A11 IMG01.jpg
−
| image              =
+
|designer=Socionext
−
| image size          =
+
|designer 2=ARM Holdings
−
| caption            =  
+
|model number=SC2A11
−
| designer           = Socionext
+
|market=Server
−
| designer 2         = ARM Holdings
+
|market 2=Networking
−
| manufacturer        =
+
|market 3=IoT
−
| model number       = SC2A11
+
|first announced=November 14, 2016
−
| part number        =
+
|first launched=2017
−
| part number 1      =
+
|frequency=1,000 MHz
−
| part number 2      =
+
|bus type=AMBA
−
| part number 3      =
+
|isa=ARMv8
−
| market             = Server
+
|isa family=ARM
−
| market 2           = Networking
+
|microarch=Cortex-A53
−
| market 3           = IoT
+
|core name=Cortex-A53
−
| first announced     = November 14, 2016
+
|technology=CMOS
−
| first launched     =
+
|word size=64 bit
−
| last order          =
+
|core count=24
−
| last shipment      =
+
|thread count=24
−
| release price      =
+
|max cpus=64
−
 
+
|max memory=64 GiB
−
| family              =
+
|tdp=5 W
−
| series              =
 
−
| locked              =  
 
−
| frequency           = 1,000 MHz
 
−
| bus type           = AMBA
 
−
| bus speed          = <!-- (Property::bus speed) -->
 
−
| bus rate            = <!-- (Property::bus rate) -->
 
−
| bus links          = <!-- ?x bus rate -->
 
−
| clock multiplier    =
 
−
 
 
−
| isa family         = ARM
 
−
| isa                = ARMv8
 
−
| microarch           = Cortex-A53
 
−
| platform            =
 
−
| chipset            =
 
−
| core name           = Cortex-A53
 
−
| core family        =
 
−
| core model          =
 
−
| core stepping      =
 
−
| transistors        =
 
−
| technology         = CMOS
 
−
| die area            = <!-- XX mm² -->
 
−
| die width          =
 
−
| die length          =
 
−
| word size           = 64 bit
 
−
| core count         = 24
 
−
| thread count       = 24
 
−
| max cpus           =  
 
−
| max memory         =
 
−
 
 
−
| electrical          = <!-- put Yes if electrical info is added -->
 
−
| power              = <!-- power consumption  -->
 
−
| v core              =
 
−
| v core tolerance    =
 
−
| v io                =
 
−
| v io tolerance      =
 
−
| v io 2              = <!-- OR ... -->
 
−
| v io 3              =
 
−
| sdp                =
 
−
| tdp                =  
 
−
| tdp typical        =
 
−
| ctdp down          =
 
−
| ctdp down frequency =
 
−
| ctdp up            =
 
−
| ctdp up frequency  =
 
−
| temp min            = <!-- use TJ/TC whenever possible instead -->
 
−
| temp max            =
 
−
| tjunc min          = <!-- .. °C -->
 
−
| tjunc max          =
 
−
| tcase min          =
 
−
| tcase max          =
 
−
| tstorage min        =
 
−
| tstorage max        =
 
−
| tambient min        =
 
−
| tambient max        =
 
−
 
 
−
| package module 1    =
 
−
| package module 2    =
 
−
 
 
−
| packaging          = <!-- put Yes if packaging info is added -->
 
−
| package 0          =
 
−
| package 0 type      =
 
−
| package 0 pins      =
 
−
| package 0 pitch    =
 
−
| package 0 width    =
 
−
| package 0 length    =
 
−
| package 0 height    =
 
−
| socket 0            =
 
−
| socket 0 type      =  
 
 
}}
 
}}
−
'''SC2A11''' is a {{arch|64}} [[tetracosa-core]] [[ARM]] system on a chip designed by [[Socionext]] for low-power servers and cloud/[[IoT]] edge computing. This chip, which incorporates 24 ultra-low power {{armh|Cortex-A53|l=arch}} cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory.
+
'''SC2A11''' is a {{arch|64}} [[tetracosa-core]] [[ARM]] system on a chip designed by [[Socionext]] for low-power servers and cloud/[[IoT]] edge computing. This chip, which incorporates 24 ultra-low power {{armh|Cortex-A53|l=arch}} cores, operates at 1 GHz and supports up to 64 GiB of DDR4-2133 ECC memory.
  
−
 
−
{{unknown features}}
 
 
== Cache ==
 
== Cache ==
 
{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A53 § Cache}}
 
{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A53 § Cache}}
 
{{cache size
 
{{cache size
−
|l1 cache = 1.5 MiB
+
|l1 cache=1.5 MiB
 
|l1i cache=768 KiB
 
|l1i cache=768 KiB
 
|l1i break=24x32 KiB
 
|l1i break=24x32 KiB
Line 108: Line 38:
 
|l1d break=24x32 KiB
 
|l1d break=24x32 KiB
 
|l1d desc=4-way set associative
 
|l1d desc=4-way set associative
−
|l2 cache=1.5 MiB
+
|l2 cache=3 MiB
−
|l2 break=2x256 KiB
+
|l2 break=12x256 KiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l3 cache=4 MiB
 
|l3 cache=4 MiB
Line 118: Line 48:
 
|type=DDR4-2133
 
|type=DDR4-2133
 
|ecc=Yes
 
|ecc=Yes
−
|max mem=
+
|max mem=64 GiB
−
|controllers=
+
|channels=2
−
|channels=1
+
|max bandwidth=31.79 GiB/s
−
|max bandwidth=15.89 GiB/s
 
 
|bandwidth schan=15.89 GiB/s
 
|bandwidth schan=15.89 GiB/s
−
|bandwidth dchan=
+
|bandwidth dchan=31.79 GiB/s
 
}}
 
}}
  
Line 141: Line 70:
  
 
== Storage ==
 
== Storage ==
−
* HSSPI
+
* SPI
 
* eMMC
 
* eMMC
 +
 +
== Block diagram ==
 +
:[[File:SC2A11 block.png|750px]]

Latest revision as of 14:00, 15 February 2019

Edit Values
Socionext SC2A11
SC2A11 IMG01.jpg
General Info
DesignerSocionext,
ARM Holdings
Model NumberSC2A11
MarketServer, Networking, IoT
IntroductionNovember 14, 2016 (announced)
2017 (launched)
General Specs
Frequency1,000 MHz
Bus typeAMBA
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A53
Core NameCortex-A53
TechnologyCMOS
Word Size64 bit
Cores24
Threads24
Max Memory64 GiB
Multiprocessing
Max SMP64-Way (Multiprocessor)
Electrical
TDP5 W

SC2A11 is a 64-bit tetracosa-core ARM system on a chip designed by Socionext for low-power servers and cloud/IoT edge computing. This chip, which incorporates 24 ultra-low power Cortex-A53 cores, operates at 1 GHz and supports up to 64 GiB of DDR4-2133 ECC memory.

Cache[edit]

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.5 MiB
1,536 KiB
1,572,864 B
L1I$768 KiB
786,432 B
0.75 MiB
24x32 KiB2-way set associative 
L1D$768 KiB
786,432 B
0.75 MiB
24x32 KiB4-way set associative 
L2$3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
  12x256 KiB16-way set associative 
L3$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
     

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Max Mem64 GiB
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes4
UART
GP I/OYes


Graphics[edit]

This SoC has no integrated graphics processing unit.

Networking[edit]

  • 2x Gigabit Ethernet Interfaces

Storage[edit]

  • SPI
  • eMMC

Block diagram[edit]

SC2A11 block.png
Retrieved from "https://en.wikichip.org/w/index.php?title=socionext/sc2a11&oldid=86610"
Facts about "SC2A11 - Socionext"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
SC2A11 - Socionext#io +
has ecc memory supporttrue +
l1$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description4-way set associative +
l1d$ size768 KiB (786,432 B, 0.75 MiB) +
l1i$ description2-way set associative +
l1i$ size768 KiB (786,432 B, 0.75 MiB) +
l2$ description16-way set associative +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
max memory bandwidth15.89 GiB/s (16,271.36 MiB/s, 17.062 GB/s, 17,061.758 MB/s, 0.0155 TiB/s, 0.0171 TB/s) +
max memory channels1 +
max pcie lanes4 +
supported memory typeDDR4-2133 +