Semiconductor & Computer Engineering
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Difference between revisions of "intel/celeron/p4505"
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{{intel title|Celeron P4505}} | {{intel title|Celeron P4505}} | ||
| − | {{ | + | {{chip |
| name = Intel Celeron P4505 | | name = Intel Celeron P4505 | ||
| no image = yes | | no image = yes | ||
| Line 11: | Line 11: | ||
| part number = CN80617004545AF | | part number = CN80617004545AF | ||
| market = Mobile | | market = Mobile | ||
| + | | market 2 = Embedded | ||
| first announced = March 28, 2010 | | first announced = March 28, 2010 | ||
| first launched = March 28, 2010 | | first launched = March 28, 2010 | ||
| Line 31: | Line 32: | ||
| cpuid = 0x20655 | | cpuid = 0x20655 | ||
| + | | isa family = x86 | ||
| + | | isa = x86-64 | ||
| microarch = Westmere | | microarch = Westmere | ||
| platform = Calpella | | platform = Calpella | ||
| Line 50: | Line 53: | ||
| max memory = 8 GiB | | max memory = 8 GiB | ||
| − | + | ||
| v core = | | v core = | ||
| v core tolerance = | | v core tolerance = | ||
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|avx=No | |avx=No | ||
|avx2=No | |avx2=No | ||
| − | + | ||
|abm=No | |abm=No | ||
|tbm=No | |tbm=No | ||
Latest revision as of 15:16, 13 December 2017
| Edit Values | ||||||||||
| Intel Celeron P4505 | ||||||||||
| General Info | ||||||||||
| Designer | Intel | |||||||||
| Manufacturer | Intel | |||||||||
| Model Number | P4505 | |||||||||
| Part Number | CN80617004545AF | |||||||||
| S-Spec | SLBQB | |||||||||
| Market | Mobile, Embedded | |||||||||
| Introduction | March 28, 2010 (announced) March 28, 2010 (launched) | |||||||||
| Shop | Amazon | |||||||||
| General Specs | ||||||||||
| Family | Celeron | |||||||||
| Series | P4000 | |||||||||
| Locked | Yes | |||||||||
| Frequency | 1,866.66 MHz | |||||||||
| Bus type | DMI 1.0 | |||||||||
| Bus rate | 1 × 2.5 GT/s | |||||||||
| Clock multiplier | 14 | |||||||||
| CPUID | 0x20655 | |||||||||
| Microarchitecture | ||||||||||
| ISA | x86-64 (x86) | |||||||||
| Microarchitecture | Westmere | |||||||||
| Platform | Calpella | |||||||||
| Chipset | Ibex Peak | |||||||||
| Core Name | Arrandale | |||||||||
| Core Family | 6 | |||||||||
| Core Model | 37 | |||||||||
| Core Stepping | C2 | |||||||||
| Process | 32 nm | |||||||||
| Transistors | 382,000,000 | |||||||||
| Technology | CMOS | |||||||||
| Die | 81 mm² | |||||||||
| Word Size | 64 bit | |||||||||
| Cores | 2 | |||||||||
| Threads | 2 | |||||||||
| Max Memory | 8 GiB | |||||||||
| Multiprocessing | ||||||||||
| Max SMP | 1-Way (Uniprocessor) | |||||||||
| Electrical | ||||||||||
| TDP | 35 W | |||||||||
| Tjunction | 0 °C – 90 °C | |||||||||
| Tstorage | -25 °C – 125 °C | |||||||||
| Packaging | ||||||||||
| ||||||||||
Celeron P4505 is a 64-bit dual-core x86 mobile microprocessor introduced by Intel in 2010. This processor operates at a frequency of 1.86 GHz and a TDP of 35 W. This MPU is manufactured on a 32 nm process based on the Westmere microarchitecture (Arrandale core). This processor incorporated the HD Graphics (Ironlake) IGP on the same package operating at a base frequency of 500.00 MHz and a burst frequency of 667.00 MHz.
Cache[edit]
- Main article: Westmere § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Graphics[edit]
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Integrated Graphics Information
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Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Celeron P4505 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron P4505 - Intel#io + |
| device id | 0x0046 + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Enhanced SpeedStep Technology +, Extended Page Tables + and Flex Memory Access + |
| has intel enhanced speedstep technology | true + |
| has intel flex memory access support | true + |
| has second level address translation support | true + |
| integrated gpu | HD Graphics (Ironlake) + |
| integrated gpu base frequency | 500 MHz (0.5 GHz, 500,000 KHz) + |
| integrated gpu designer | Intel + |
| integrated gpu execution units | 12 + |
| integrated gpu max frequency | 667 MHz (0.667 GHz, 667,000 KHz) + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | 8-way set associative + |
| l3$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| max memory bandwidth | 15.88 GiB/s (16,261.12 MiB/s, 17.051 GB/s, 17,051.02 MB/s, 0.0155 TiB/s, 0.0171 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 16 + |
| supported memory type | DDR3-1066 + |