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Difference between revisions of "intel/celeron/u3400"
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{{intel title|Celeron U3400}} | {{intel title|Celeron U3400}} | ||
− | {{ | + | {{chip |
| name = Intel Celeron U3400 | | name = Intel Celeron U3400 | ||
| no image = yes | | no image = yes | ||
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| cpuid = 0x20655 | | cpuid = 0x20655 | ||
+ | | isa family = x86 | ||
+ | | isa = x86-64 | ||
| microarch = Westmere | | microarch = Westmere | ||
| platform = Calpella | | platform = Calpella | ||
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| max memory = 8 GiB | | max memory = 8 GiB | ||
− | + | ||
| v core = | | v core = | ||
| v core tolerance = | | v core tolerance = | ||
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| intel clear video = Yes | | intel clear video = Yes | ||
| intel clear video hd = | | intel clear video hd = | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=No | ||
+ | |sse42=No | ||
+ | |sse4a=No | ||
+ | |avx=No | ||
+ | |avx2=No | ||
+ | |||
+ | |abm=No | ||
+ | |tbm=No | ||
+ | |bmi1=No | ||
+ | |bmi2=No | ||
+ | |fma3=No | ||
+ | |fma4=No | ||
+ | |aes=No | ||
+ | |rdrand=No | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=No | ||
+ | |clmul=No | ||
+ | |f16c=No | ||
+ | |tbt1=No | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |flex=Yes | ||
+ | |fastmem=Yes | ||
+ | |isrt=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=No | ||
+ | |ht=No | ||
+ | |vpro=No | ||
+ | |vtx=No | ||
+ | |vtd=No | ||
+ | |ept=No | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdv=No | ||
+ | |rvi=No | ||
}} | }} |
Latest revision as of 15:16, 13 December 2017
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Intel Celeron U3400 | ||||||||||
General Info | ||||||||||
Designer | Intel | |||||||||
Manufacturer | Intel | |||||||||
Model Number | U3400 | |||||||||
Part Number | CN80617006039AA | |||||||||
S-Spec | SLBUE | |||||||||
Market | Mobile | |||||||||
Introduction | May 24, 2010 (announced) May 24, 2010 (launched) | |||||||||
Shop | Amazon | |||||||||
General Specs | ||||||||||
Family | Celeron | |||||||||
Series | P3000 | |||||||||
Locked | Yes | |||||||||
Frequency | 1,066.66 MHz | |||||||||
Bus type | DMI 1.0 | |||||||||
Bus rate | 1 × 2.5 GT/s | |||||||||
Clock multiplier | 8 | |||||||||
CPUID | 0x20655 | |||||||||
Microarchitecture | ||||||||||
ISA | x86-64 (x86) | |||||||||
Microarchitecture | Westmere | |||||||||
Platform | Calpella | |||||||||
Chipset | Ibex Peak | |||||||||
Core Name | Arrandale | |||||||||
Core Family | 6 | |||||||||
Core Model | 37 | |||||||||
Core Stepping | K0 | |||||||||
Process | 32 nm | |||||||||
Transistors | 382,000,000 | |||||||||
Technology | CMOS | |||||||||
Die | 81 mm² | |||||||||
Word Size | 64 bit | |||||||||
Cores | 2 | |||||||||
Threads | 2 | |||||||||
Max Memory | 8 GiB | |||||||||
Multiprocessing | ||||||||||
Max SMP | 1-Way (Uniprocessor) | |||||||||
Electrical | ||||||||||
TDP | 18 W | |||||||||
Tjunction | 0 °C – 90 °C | |||||||||
Tstorage | -25 °C – 125 °C | |||||||||
Packaging | ||||||||||
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Celeron U3400 is a 64-bit dual-core x86 mobile microprocessor introduced by Intel in 2010. This processor operates at a frequency of 1.06 GHz and a TDP of 18 W. This MPU is manufactured on a 32 nm process based on the Westmere microarchitecture (Arrandale core). This processor incorporated the HD Graphics (Ironlake) IGP on the same package operating at a base frequency of 166.00 MHz and a burst frequency of 500.00 MHz.
Cache[edit]
- Main article: Westmere § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Graphics[edit]
Integrated Graphics Information
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Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Facts about "Celeron U3400 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron U3400 - Intel#io + |
device id | 0x0046 + |
has ecc memory support | false + |
has feature | Enhanced SpeedStep Technology + and Flex Memory Access + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
integrated gpu | HD Graphics (Ironlake) + |
integrated gpu base frequency | 166 MHz (0.166 GHz, 166,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 12 + |
integrated gpu max frequency | 500 MHz (0.5 GHz, 500,000 KHz) + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 8-way set associative + |
l3$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
supported memory type | DDR3-800 + |