From WikiChip
Difference between revisions of "intel/core i3/i3-390m"
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{{intel title|Core i3-390M}} | {{intel title|Core i3-390M}} | ||
− | {{ | + | {{chip |
| name = Intel Core i3-390M | | name = Intel Core i3-390M | ||
| no image = yes | | no image = yes | ||
Line 10: | Line 10: | ||
| model number = i3-390M | | model number = i3-390M | ||
| part number = CP80617005487AB | | part number = CP80617005487AB | ||
− | | part number | + | | part number 2 = CN80617005487AB |
| market = Mobile | | market = Mobile | ||
| first announced = January 11, 2011 | | first announced = January 11, 2011 | ||
Line 32: | Line 32: | ||
| cpuid = 0x20655 | | cpuid = 0x20655 | ||
+ | | isa family = x86 | ||
+ | | isa = x86-64 | ||
| microarch = Westmere | | microarch = Westmere | ||
| platform = Calpella | | platform = Calpella | ||
Line 51: | Line 53: | ||
| max memory = 8 GiB | | max memory = 8 GiB | ||
− | + | ||
| v core = | | v core = | ||
| v core tolerance = | | v core tolerance = | ||
Line 105: | Line 107: | ||
|bandwidth dchan=15.88 GiB/s | |bandwidth dchan=15.88 GiB/s | ||
|pae=36 bit | |pae=36 bit | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 2.0 | ||
+ | | pcie lanes = 16 | ||
+ | | pcie config = 1x16 | ||
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | {{integrated graphics | ||
+ | | gpu = HD Graphics (Ironlake) | ||
+ | | device id = 0x0046 | ||
+ | | designer = Intel | ||
+ | | execution units = 12 | ||
+ | | max displays = 2 | ||
+ | | max memory = | ||
+ | | frequency = 500 MHz | ||
+ | | max frequency = 667 MHz | ||
+ | |||
+ | | directx ver = 10.1 | ||
+ | | opengl ver = 2.1 | ||
+ | |||
+ | | features = Yes | ||
+ | | intel quick sync = | ||
+ | | intel intru 3d = | ||
+ | | intel insider = | ||
+ | | intel widi = | ||
+ | | intel fdi = Yes | ||
+ | | intel clear video = Yes | ||
+ | | intel clear video hd = Yes | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=No | ||
+ | |avx2=No | ||
+ | |||
+ | |abm=No | ||
+ | |tbm=No | ||
+ | |bmi1=No | ||
+ | |bmi2=No | ||
+ | |fma3=No | ||
+ | |fma4=No | ||
+ | |aes=No | ||
+ | |rdrand=No | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=No | ||
+ | |clmul=No | ||
+ | |f16c=No | ||
+ | |tbt1=No | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |flex=Yes | ||
+ | |fastmem=Yes | ||
+ | |isrt=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=No | ||
+ | |ht=Yes | ||
+ | |vpro=No | ||
+ | |vtx=Yes | ||
+ | |vtd=No | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdv=No | ||
+ | |rvi=No | ||
}} | }} |
Latest revision as of 15:17, 13 December 2017
Edit Values | ||||||||||||
Intel Core i3-390M | ||||||||||||
General Info | ||||||||||||
Designer | Intel | |||||||||||
Manufacturer | Intel | |||||||||||
Model Number | i3-390M | |||||||||||
Part Number | CP80617005487AB, CN80617005487AB | |||||||||||
S-Spec | SLC24, SLC25 | |||||||||||
Market | Mobile | |||||||||||
Introduction | January 11, 2011 (announced) January 11, 2011 (launched) | |||||||||||
Shop | Amazon | |||||||||||
General Specs | ||||||||||||
Family | Core i3 | |||||||||||
Series | i3-300 | |||||||||||
Locked | Yes | |||||||||||
Frequency | 2,666.66 MHz | |||||||||||
Bus type | DMI 1.0 | |||||||||||
Bus rate | 1 × 2.5 GT/s | |||||||||||
Clock multiplier | 20 | |||||||||||
CPUID | 0x20655 | |||||||||||
Microarchitecture | ||||||||||||
ISA | x86-64 (x86) | |||||||||||
Microarchitecture | Westmere | |||||||||||
Platform | Calpella | |||||||||||
Chipset | Ibex Peak | |||||||||||
Core Name | Arrandale | |||||||||||
Core Family | 6 | |||||||||||
Core Model | 37 | |||||||||||
Core Stepping | K0 | |||||||||||
Process | 32 nm | |||||||||||
Transistors | 382,000,000 | |||||||||||
Technology | CMOS | |||||||||||
Die | 81 mm² | |||||||||||
Word Size | 64 bit | |||||||||||
Cores | 2 | |||||||||||
Threads | 4 | |||||||||||
Max Memory | 8 GiB | |||||||||||
Multiprocessing | ||||||||||||
Max SMP | 1-Way (Uniprocessor) | |||||||||||
Electrical | ||||||||||||
TDP | 35 W | |||||||||||
Tjunction | 0 °C – 105 °C | |||||||||||
Tstorage | -25 °C – 125 °C | |||||||||||
Packaging | ||||||||||||
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Core i3-390M is a 64-bit dual-core x86 mobile microprocessor introduced by Intel in 2010. This processor operates at a frequency of 2.66 GHz and a TDP of 35 W. This MPU is manufactured on a 32 nm process based on the Westmere microarchitecture (Arrandale core). This processor incorporated the HD Graphics (Ironlake) IGP on the same package operating at a base frequency of 500.00 MHz and a burst frequency of 667.00 MHz.
Cache[edit]
- Main article: Westmere § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Graphics[edit]
Integrated Graphics Information
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Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Facts about "Core i3-390M - Intel"
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |