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Difference between revisions of "intel/xeon e5/e5-2679 v4"
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{{intel title|Xeon E5-2679 v4}} | {{intel title|Xeon E5-2679 v4}} | ||
| − | {{ | + | {{chip |
| name = Xeon E5-2679 v4 | | name = Xeon E5-2679 v4 | ||
| no image = Yes | | no image = Yes | ||
| Line 10: | Line 10: | ||
| model number = E5-2679 v4 | | model number = E5-2679 v4 | ||
| part number = CM8066002647800 | | part number = CM8066002647800 | ||
| − | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Server | | market = Server | ||
| first announced = June 20, 2016 | | first announced = June 20, 2016 | ||
| Line 26: | Line 26: | ||
| turbo frequency = Yes | | turbo frequency = Yes | ||
| turbo frequency1 = 3,300 MHz | | turbo frequency1 = 3,300 MHz | ||
| − | | turbo frequency2 = | + | | turbo frequency2 = 3,300 MHz |
| + | | turbo frequency3 = 3,200 MHz | ||
| + | | turbo frequency4 = 3,200 MHz | ||
| + | | turbo frequency5 = 3,200 MHz | ||
| + | | turbo frequency6 = 3,200 MHz | ||
| + | | turbo frequency7 = 3,200 MHz | ||
| + | | turbo frequency8 = 3,200 MHz | ||
| + | | turbo frequency9 = 3,200 MHz | ||
| + | | turbo frequency10 = 3,200 MHz | ||
| + | | turbo frequency11 = 3,200 MHz | ||
| + | | turbo frequency12 = 3,200 MHz | ||
| + | | turbo frequency13 = 3,200 MHz | ||
| + | | turbo frequency14 = 3,200 MHz | ||
| + | | turbo frequency15 = 3,200 MHz | ||
| + | | turbo frequency16 = 3,200 MHz | ||
| + | | turbo frequency17 = 3,200 MHz | ||
| + | | turbo frequency18 = 3,200 MHz | ||
| + | | turbo frequency19 = 3,200 MHz | ||
| + | | turbo frequency20 = 3,200 MHz | ||
| bus type = QPI | | bus type = QPI | ||
| bus speed = 4,800 MHz | | bus speed = 4,800 MHz | ||
| Line 54: | Line 72: | ||
| max memory = 1,536 GiB | | max memory = 1,536 GiB | ||
| − | + | ||
| v core = 1.82 V | | v core = 1.82 V | ||
| v core tolerance = | | v core tolerance = | ||
| Line 123: | Line 141: | ||
== Expansions == | == Expansions == | ||
| − | {{ | + | {{expansions |
| pcie revision = 3.0 | | pcie revision = 3.0 | ||
| pcie lanes = 40 | | pcie lanes = 40 | ||
| Line 132: | Line 150: | ||
== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| em64t = Yes | | em64t = Yes | ||
| nx = Yes | | nx = Yes | ||
Latest revision as of 15:28, 13 December 2017
| Edit Values | |
| Xeon E5-2679 v4 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | E5-2679 v4 |
| Part Number | CM8066002647800 |
| S-Spec | SR2K5 |
| Market | Server |
| Introduction | June 20, 2016 (announced) June 20, 2016 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | Xeon E5 |
| Series | E5-2000 |
| Locked | Yes |
| Frequency | 2,500 MHz |
| Turbo Frequency | Yes |
| Turbo Frequency | 3,300 MHz (1 core), 3,300 MHz (2 cores), 3,200 MHz (3 cores), 3,200 MHz (4 cores), 3,200 MHz (5 cores), 3,200 MHz (6 cores), 3,200 MHz (7 cores), 3,200 MHz (8 cores), 3,200 MHz (9 cores), 3,200 MHz (10 cores), 3,200 MHz (11 cores), 3,200 MHz (12 cores), 3,200 MHz (13 cores), 3,200 MHz (14 cores), 3,200 MHz (15 cores), 3,200 MHz (16 cores), 3,200 MHz (17 cores), 3,200 MHz (18 cores), 3,200 MHz (19 cores), 3,200 MHz (20 cores) |
| Bus type | QPI |
| Bus speed | 4,800 MHz |
| Bus rate | 2 × 9.6 GT/s |
| Clock multiplier | 25 |
| CPUID | 406F1 |
| Microarchitecture | |
| Microarchitecture | Broadwell |
| Platform | Grantley EP 2S |
| Chipset | C610 Series |
| Core Name | Broadwell EP |
| Core Family | 6 |
| Core Model | 4F |
| Core Stepping | B0 |
| Process | 14 nm |
| Transistors | 7,200,000,000 |
| Technology | CMOS |
| Die | 456.12 mm² |
| Word Size | 64 bit |
| Cores | 20 |
| Threads | 40 |
| Max Memory | 1,536 GiB |
| Multiprocessing | |
| Max SMP | 2-Way (Multiprocessor) |
| Electrical | |
| Vcore | 1.82 V |
| VI/O | 1.2 V ± 3% |
| TDP | 200 W |
| Tcase | 0 °C – ? °C |
| Tstorage | -25 °C – 125 °C |
The Xeon E5-2679 v4 is a 64-bit icosa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for 2S environments. Operating at 2.5 GHz with a turbo boost frequency of 3.3 GHz for a single active core, this MPU has a TDP of 200 W and is manufactured on a 14 nm process (based on Broadwell).
Cache[edit]
- Main article: Broadwell § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 640 KiB 655,360 B 0.625 MiB |
20x32 KiB 8-way set associative (per core, write-back) |
| L1D$ | 640 KiB 655,360 B 0.625 MiB |
20x32 KiB 8-way set associative (per core, write-back) |
| L2$ | 5 MiB 5,120 KiB 5,242,880 B 0.00488 GiB |
20x256 KiB 8-way set associative (per core, write-back) |
| L3$ | 50 MiB 51,200 KiB 52,428,800 B 0.0488 GiB |
20x2.5 MiB 20-way set associative (shared, per core, write-back) |
Graphics[edit]
This microprocessor has no integrated graphics processing unit.
Memory controller[edit]
| Integrated Memory Controller | |
| Type | DDR4-2400 |
| Controllers | 1 |
| Channels | 4 |
| ECC Support | Yes |
| Max bandwidth | 71.53 GiB/s |
| Bandwidth (single) | 17.88 GiB/s |
| Bandwidth (dual) | 35.76 GiB/s |
| Max memory | 1,536 GiB |
| Physical Address Extensions | 46 bit |
Expansions[edit]
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Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Xeon E5-2679 v4 - Intel"
| l1d$ description | 8-way set associative + |
| l1d$ size | 640 KiB (655,360 B, 0.625 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 640 KiB (655,360 B, 0.625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 5 MiB (5,120 KiB, 5,242,880 B, 0.00488 GiB) + |
| l3$ description | 20-way set associative + |
| l3$ size | 50 MiB (51,200 KiB, 52,428,800 B, 0.0488 GiB) + |