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{{intel title|Xeon E5-2618L v4}}
 
{{intel title|Xeon E5-2618L v4}}
{{mpu
+
{{chip
 
| name                = Xeon E5-2618L v4
 
| name                = Xeon E5-2618L v4
 
| no image            = Yes
 
| no image            = Yes
Line 10: Line 10:
 
| model number        = E5-2618L v4
 
| model number        = E5-2618L v4
 
| part number        = CM8066002061300
 
| part number        = CM8066002061300
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Embedded
 
| market              = Embedded
 
| first announced    = June 20, 2016
 
| first announced    = June 20, 2016
Line 26: Line 26:
 
| turbo frequency    = Yes
 
| turbo frequency    = Yes
 
| turbo frequency1    = 3,200 MHz
 
| turbo frequency1    = 3,200 MHz
| turbo frequency2    =  
+
| turbo frequency2    = 3,200 MHz
 +
| turbo frequency3    = 3,000 MHz
 +
| turbo frequency4    = 2,900 MHz
 +
| turbo frequency5    = 2,800 MHz
 +
| turbo frequency6    = 2,700 MHz
 +
| turbo frequency7    = 2,600 MHz
 +
| turbo frequency8    = 2,500 MHz
 +
| turbo frequency9    = 2,400 MHz
 +
| turbo frequency10  = 2,400 MHz
 
| bus type            = QPI
 
| bus type            = QPI
 
| bus speed          = 4,000 MHz
 
| bus speed          = 4,000 MHz
Line 37: Line 45:
 
| cpuid              = 406F1
 
| cpuid              = 406F1
  
 +
| isa family          = x86
 +
| isa                = x86-64
 
| microarch          = Broadwell
 
| microarch          = Broadwell
 
| platform            = Grantley EP 2S
 
| platform            = Grantley EP 2S
Line 54: Line 64:
 
| max memory          = 1,536 GiB
 
| max memory          = 1,536 GiB
  
| electrical          = Yes
+
 
 
| v core              = 1.82 V
 
| v core              = 1.82 V
 
| v core tolerance    =  
 
| v core tolerance    =  
Line 82: Line 92:
 
| socket 0            = LGA-2011-v3
 
| socket 0            = LGA-2011-v3
 
| socket 0 type      = LGA
 
| socket 0 type      = LGA
 +
}}
 +
The '''Xeon E5-2618L v4''' is a {{arch|64}} [[deca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for low-power 2S environments (1U square form factor). Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 3.2 GHz for a single active core, this MPU has a TDP of 75 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
 +
{{cache info
 +
|l1i cache=320 KiB
 +
|l1i break=10x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1i extra=(per core, write-back)
 +
|l1d cache=320 KiB
 +
|l1d break=10x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d extra=(per core, write-back)
 +
|l2 cache=2.5 MiB
 +
|l2 break=10x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 extra=(per core, write-back)
 +
|l3 cache=25 MiB
 +
|l3 break=10x2.5 MiB
 +
|l3 desc=20-way set associative
 +
|l3 extra=(shared, per core, write-back)
 +
}}
 +
 +
== Graphics ==
 +
This microprocessor has no [[integrated graphics processing unit]].
 +
 +
== Memory controller ==
 +
{{integrated memory controller
 +
| type              = DDR4-2133
 +
| controllers        = 1
 +
| channels          = 4
 +
| ecc support        = Yes
 +
| max bandwidth      = 63.58 GiB/s
 +
| bandwidth schan    = 15.89 GiB/s
 +
| bandwidth dchan    = 31.79 GiB/s
 +
| max memory        = 1,536 GiB
 +
| pae                = 46 bit
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 40
 +
| pcie config        = x4
 +
| pcie config 1      = x8
 +
| pcie config 2      = x16
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
| em64t      = Yes
 +
| nx          = Yes
 +
| txt        = Yes
 +
| tsx        = Yes
 +
| vpro        = Yes
 +
| ht          = Yes
 +
| tbt1        =
 +
| tbt2        = Yes
 +
| tbmt3      =
 +
| bpt        =
 +
| vt-x        = Yes
 +
| vt-d        = Yes
 +
| ept        = Yes
 +
| mmx        = Yes
 +
| sse        = Yes
 +
| sse2        = Yes
 +
| sse3        = Yes
 +
| ssse3      = Yes
 +
| sse4.1      = Yes
 +
| sse4.2      = Yes
 +
| aes        = Yes
 +
| pclmul      = Yes
 +
| avx        = Yes
 +
| avx2        = Yes
 +
| bmi        = Yes
 +
| bmi1        = Yes
 +
| bmi2        = Yes
 +
| f16c        = Yes
 +
| fma3        = Yes
 +
| mpx        =
 +
| sgx        =
 +
| eist        = Yes
 +
| secure key  = Yes
 +
| os guard    = Yes
 +
| intel at    =
 +
| intel ipt  =
 
}}
 
}}

Latest revision as of 16:27, 13 December 2017

Edit Values
Xeon E5-2618L v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-2618L v4
Part NumberCM8066002061300
S-SpecSR2PE
MarketEmbedded
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
Release Price$779
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-2000
LockedYes
Frequency2,200 MHz
Turbo FrequencyYes
Turbo Frequency3,200 MHz (1 core),
3,200 MHz (2 cores),
3,000 MHz (3 cores),
2,900 MHz (4 cores),
2,800 MHz (5 cores),
2,700 MHz (6 cores),
2,600 MHz (7 cores),
2,500 MHz (8 cores),
2,400 MHz (9 cores),
2,400 MHz (10 cores)
Bus typeQPI
Bus speed4,000 MHz
Bus rate2 × 8 GT/s
Clock multiplier22
CPUID406F1
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureBroadwell
PlatformGrantley EP 2S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingR0
Process14 nm
Transistors3,200,000,000
TechnologyCMOS
Die246.24 mm²
Word Size64 bit
Cores10
Threads20
Max Memory1,536 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP75 W
Tcase0 °C – 87 °C
Tstorage-25 °C – 125 °C

The Xeon E5-2618L v4 is a 64-bit deca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for low-power 2S environments (1U square form factor). Operating at 2.2 GHz with a turbo boost frequency of 3.2 GHz for a single active core, this MPU has a TDP of 75 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 320 KiB
327,680 B
0.313 MiB
10x32 KiB 8-way set associative (per core, write-back)
L1D$ 320 KiB
327,680 B
0.313 MiB
10x32 KiB 8-way set associative (per core, write-back)
L2$ 2.5 MiB
2,560 KiB
2,621,440 B
0.00244 GiB
10x256 KiB 8-way set associative (per core, write-back)
L3$ 25 MiB
25,600 KiB
26,214,400 B
0.0244 GiB
10x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2133
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 63.58 GiB/s
Bandwidth (single) 15.89 GiB/s
Bandwidth (dual) 31.79 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

l1d$ description8-way set associative +
l1d$ size320 KiB (327,680 B, 0.313 MiB) +
l1i$ description8-way set associative +
l1i$ size320 KiB (327,680 B, 0.313 MiB) +
l2$ description8-way set associative +
l2$ size2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) +
l3$ description20-way set associative +
l3$ size25 MiB (25,600 KiB, 26,214,400 B, 0.0244 GiB) +