From WikiChip
Difference between revisions of "intel/xeon e5/e5-2667 v4"
< intel‎ | xeon e5

(+features)
(→‎Cache)
 
(9 intermediate revisions by 2 users not shown)
Line 1: Line 1:
 
{{intel title|Xeon E5-2667 v4}}
 
{{intel title|Xeon E5-2667 v4}}
−
{{mpu
+
{{chip
 
| name                = Xeon E5-2667 v4
 
| name                = Xeon E5-2667 v4
 
| no image            = Yes
 
| no image            = Yes
Line 10: Line 10:
 
| model number        = E5-2667 v4
 
| model number        = E5-2667 v4
 
| part number        = CM8066002041900
 
| part number        = CM8066002041900
−
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Server
 
| market              = Server
 
| first announced    = June 20, 2016
 
| first announced    = June 20, 2016
Line 26: Line 26:
 
| turbo frequency    = Yes
 
| turbo frequency    = Yes
 
| turbo frequency1    = 3,600 MHz
 
| turbo frequency1    = 3,600 MHz
−
| turbo frequency2    =  
+
| turbo frequency2    = 3,600 MHz
 +
| turbo frequency3    = 3,500 MHz
 +
| turbo frequency4    = 3,500 MHz
 +
| turbo frequency5    = 3,500 MHz
 +
| turbo frequency6    = 3,500 MHz
 +
| turbo frequency7    = 3,500 MHz
 +
| turbo frequency8    = 3,500 MHz
 
| bus type            = QPI
 
| bus type            = QPI
 
| bus speed          = 4,800 MHz
 
| bus speed          = 4,800 MHz
Line 34: Line 40:
 
| s-spec              = SR2P5
 
| s-spec              = SR2P5
 
| s-spec es          =  
 
| s-spec es          =  
−
| s-spec qs          =  
+
| s-spec qs          = QKF0
 
| cpuid              = 406F1
 
| cpuid              = 406F1
  
 +
| isa family          = x86
 +
| isa                = x86-64
 
| microarch          = Broadwell
 
| microarch          = Broadwell
 
| platform            = Grantley EP 2S
 
| platform            = Grantley EP 2S
Line 54: Line 62:
 
| max memory          = 1,536 GiB
 
| max memory          = 1,536 GiB
  
−
| electrical          = Yes
+
 
 
| v core              = 1.82 V
 
| v core              = 1.82 V
 
| v core tolerance    =  
 
| v core tolerance    =  
Line 101: Line 109:
 
|l2 extra=(per core, write-back)
 
|l2 extra=(per core, write-back)
 
|l3 cache=25 MiB
 
|l3 cache=25 MiB
−
|l3 break=8x3.125 MiB
+
|l3 break=10x2.5 MiB
 
|l3 desc=20-way set associative
 
|l3 desc=20-way set associative
 
|l3 extra=(shared, per core, write-back)
 
|l3 extra=(shared, per core, write-back)
Line 120: Line 128:
 
| max memory        = 1,536 GiB
 
| max memory        = 1,536 GiB
 
| pae                = 46 bit
 
| pae                = 46 bit
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 40
 +
| pcie config        = x4
 +
| pcie config 1      = x8
 +
| pcie config 2      = x16
 
}}
 
}}
  
 
== Features ==  
 
== Features ==  
−
{{mpu features
+
{{x86 features
 
| em64t      = Yes
 
| em64t      = Yes
 
| nx          = Yes
 
| nx          = Yes

Latest revision as of 12:13, 1 August 2019

Edit Values
Xeon E5-2667 v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-2667 v4
Part NumberCM8066002041900
S-SpecSR2P5
QKF0 (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
Release Price$2057.00
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-2000
LockedYes
Frequency3,200 MHz
Turbo FrequencyYes
Turbo Frequency3,600 MHz (1 core),
3,600 MHz (2 cores),
3,500 MHz (3 cores),
3,500 MHz (4 cores),
3,500 MHz (5 cores),
3,500 MHz (6 cores),
3,500 MHz (7 cores),
3,500 MHz (8 cores)
Bus typeQPI
Bus speed4,800 MHz
Bus rate2 × 9.6 GT/s
Clock multiplier32
CPUID406F1
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureBroadwell
PlatformGrantley EP 2S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingR0
Process14 nm
Transistors3,200,000,000
TechnologyCMOS
Die246.24 mm²
Word Size64 bit
Cores8
Threads16
Max Memory1,536 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP135 W
Tcase0 °C – 78 °C
Tstorage-25 °C – 125 °C

The Xeon E5-2667 v4 is a 64-bit octa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for frequency-optimized 2S environments (2U square form factor). Operating at 3.2 GHz with a turbo boost frequency of 3.6 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core, write-back)
L1D$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core, write-back)
L2$ 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
8x256 KiB 8-way set associative (per core, write-back)
L3$ 25 MiB
25,600 KiB
26,214,400 B
0.0244 GiB
10x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2667_v4&oldid=92618"
Facts about "Xeon E5-2667 v4 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ description20-way set associative +
l3$ size25 MiB (25,600 KiB, 26,214,400 B, 0.0244 GiB) +