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Difference between revisions of "intel/xeon e5/e5-2660 v4"
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{{intel title|Xeon E5-2660 v4}}
 
{{intel title|Xeon E5-2660 v4}}
−
{{mpu
+
{{chip
 
| name                = Xeon E5-2660 v4
 
| name                = Xeon E5-2660 v4
 
| no image            = Yes
 
| no image            = Yes
Line 10: Line 10:
 
| model number        = E5-2660 v4
 
| model number        = E5-2660 v4
 
| part number        = CM8066002031201
 
| part number        = CM8066002031201
−
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Server
 
| market              = Server
 
| first announced    = June 20, 2016
 
| first announced    = June 20, 2016
Line 26: Line 26:
 
| turbo frequency    = Yes
 
| turbo frequency    = Yes
 
| turbo frequency1    = 3,200 MHz
 
| turbo frequency1    = 3,200 MHz
−
| turbo frequency2    =  
+
| turbo frequency2    = 3,200 MHz
 +
| turbo frequency3    = 3,000 MHz
 +
| turbo frequency4    = 2,900 MHz
 +
| turbo frequency5    = 2,800 MHz
 +
| turbo frequency6    = 2,700 MHz
 +
| turbo frequency7    = 2,600 MHz
 +
| turbo frequency8    = 2,500 MHz
 +
| turbo frequency9    = 2,400 MHz
 +
| turbo frequency10  = 2,400 MHz
 +
| turbo frequency11  = 2,400 MHz
 +
| turbo frequency12  = 2,400 MHz
 +
| turbo frequency13  = 2,400 MHz
 +
| turbo frequency14  = 2,400 MHz
 
| bus type            = QPI
 
| bus type            = QPI
 
| bus speed          = 4,800 MHz
 
| bus speed          = 4,800 MHz
Line 34: Line 46:
 
| s-spec              = SR2N4
 
| s-spec              = SR2N4
 
| s-spec es          =  
 
| s-spec es          =  
−
| s-spec qs          =  
+
| s-spec qs          = QK8Z
 +
| s-spec qs 2        = QK90
 
| cpuid              = 406F1
 
| cpuid              = 406F1
  
Line 54: Line 67:
 
| max memory          = 1,536 GiB
 
| max memory          = 1,536 GiB
  
−
| electrical          = Yes
+
 
 
| v core              = 1.82 V
 
| v core              = 1.82 V
 
| v core tolerance    =  
 
| v core tolerance    =  
Line 120: Line 133:
 
| max memory        = 1,536 GiB
 
| max memory        = 1,536 GiB
 
| pae                = 46 bit
 
| pae                = 46 bit
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 40
 +
| pcie config        = x4
 +
| pcie config 1      = x8
 +
| pcie config 2      = x16
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
| em64t      = Yes
 +
| nx          = Yes
 +
| txt        = Yes
 +
| tsx        = Yes
 +
| vpro        = Yes
 +
| ht          = Yes
 +
| tbt1        =
 +
| tbt2        = Yes
 +
| tbmt3      =
 +
| bpt        =
 +
| vt-x        = Yes
 +
| vt-d        = Yes
 +
| ept        = Yes
 +
| mmx        = Yes
 +
| sse        = Yes
 +
| sse2        = Yes
 +
| sse3        = Yes
 +
| ssse3      = Yes
 +
| sse4.1      = Yes
 +
| sse4.2      = Yes
 +
| aes        = Yes
 +
| pclmul      = Yes
 +
| avx        = Yes
 +
| avx2        = Yes
 +
| bmi        = Yes
 +
| bmi1        = Yes
 +
| bmi2        = Yes
 +
| f16c        = Yes
 +
| fma3        = Yes
 +
| mpx        =
 +
| sgx        =
 +
| eist        = Yes
 +
| secure key  = Yes
 +
| os guard    = Yes
 +
| intel at    =
 +
| intel ipt  =
 
}}
 
}}

Latest revision as of 15:27, 13 December 2017

Edit Values
Xeon E5-2660 v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-2660 v4
Part NumberCM8066002031201
S-SpecSR2N4
QK8Z (QS), QK90 (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
Release Price$1445.00
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-2000
LockedYes
Frequency2,000 MHz
Turbo FrequencyYes
Turbo Frequency3,200 MHz (1 core),
3,200 MHz (2 cores),
3,000 MHz (3 cores),
2,900 MHz (4 cores),
2,800 MHz (5 cores),
2,700 MHz (6 cores),
2,600 MHz (7 cores),
2,500 MHz (8 cores),
2,400 MHz (9 cores),
2,400 MHz (10 cores),
2,400 MHz (11 cores),
2,400 MHz (12 cores),
2,400 MHz (13 cores),
2,400 MHz (14 cores)
Bus typeQPI
Bus speed4,800 MHz
Bus rate2 × 9.6 GT/s
Clock multiplier20
CPUID406F1
Microarchitecture
MicroarchitectureBroadwell
PlatformGrantley EP 2S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingM0
Process14 nm
Transistors4,700,000,000
TechnologyCMOS
Die306.18 mm²
Word Size64 bit
Cores14
Threads28
Max Memory1,536 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP105 W
Tcase0 °C – 79 °C
Tstorage-25 °C – 125 °C

The Xeon E5-2660 v4 is a 64-bit tetradeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for advanced 2S environments. Operating at 2 GHz with a turbo boost frequency of 3.2 GHz for a single active core, this MPU has a TDP of 105 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 448 KiB
458,752 B
0.438 MiB
14x32 KiB 8-way set associative (per core, write-back)
L1D$ 448 KiB
458,752 B
0.438 MiB
14x32 KiB 8-way set associative (per core, write-back)
L2$ 3.5 MiB
3,584 KiB
3,670,016 B
0.00342 GiB
14x256 KiB 8-way set associative (per core, write-back)
L3$ 35 MiB
35,840 KiB
36,700,160 B
0.0342 GiB
14x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2660_v4&oldid=70994"
Facts about "Xeon E5-2660 v4 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size448 KiB (458,752 B, 0.438 MiB) +
l1i$ description8-way set associative +
l1i$ size448 KiB (458,752 B, 0.438 MiB) +
l2$ description8-way set associative +
l2$ size3.5 MiB (3,584 KiB, 3,670,016 B, 0.00342 GiB) +
l3$ description20-way set associative +
l3$ size35 MiB (35,840 KiB, 36,700,160 B, 0.0342 GiB) +