From WikiChip
Difference between revisions of "intel/xeon e5/e5-2698 v4"
< intel‎ | xeon e5

m (Bot: moving all {{mpu}} to {{chip}})
 
(16 intermediate revisions by 4 users not shown)
Line 1: Line 1:
 
{{intel title|Xeon E5-2698 v4}}
 
{{intel title|Xeon E5-2698 v4}}
−
{{mpu
+
{{chip
 
| name                = Xeon E5-2698 v4
 
| name                = Xeon E5-2698 v4
 
| no image            = Yes
 
| no image            = Yes
Line 10: Line 10:
 
| model number        = E5-2698 v4
 
| model number        = E5-2698 v4
 
| part number        = CM8066002024000
 
| part number        = CM8066002024000
−
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Server
 
| market              = Server
 
| first announced    = June 20, 2016
 
| first announced    = June 20, 2016
Line 26: Line 26:
 
| turbo frequency    = Yes
 
| turbo frequency    = Yes
 
| turbo frequency1    = 3,600 MHz
 
| turbo frequency1    = 3,600 MHz
−
| turbo frequency2    =  
+
| turbo frequency2    = 3,600 MHz
 +
| turbo frequency3    = 3,400 MHz
 +
| turbo frequency4    = 3,300 MHz
 +
| turbo frequency5    = 3,200 MHz
 +
| turbo frequency6    = 3,100 MHz
 +
| turbo frequency7    = 3,000 MHz
 +
| turbo frequency8    = 2,900 MHz
 +
| turbo frequency9    = 2,800 MHz
 +
| turbo frequency10  = 2,700 MHz
 +
| turbo frequency11  = 2,700 MHz
 +
| turbo frequency12  = 2,700 MHz
 +
| turbo frequency13  = 2,700 MHz
 +
| turbo frequency14  = 2,700 MHz
 +
| turbo frequency15  = 2,700 MHz
 +
| turbo frequency16  = 2,700 MHz
 +
| turbo frequency17  = 2,700 MHz
 +
| turbo frequency18  = 2,700 MHz
 +
| turbo frequency19  = 2,700 MHz
 +
| turbo frequency20  = 2,700 MHz
 
| bus type            = QPI
 
| bus type            = QPI
 
| bus speed          = 4,800 MHz
 
| bus speed          = 4,800 MHz
Line 34: Line 52:
 
| s-spec              = SR2JW
 
| s-spec              = SR2JW
 
| s-spec es          =  
 
| s-spec es          =  
−
| s-spec qs          =  
+
| s-spec qs          = QK11
 +
| s-spec qs 2        = QK7M
 
| cpuid              = 406F1
 
| cpuid              = 406F1
  
Line 54: Line 73:
 
| max memory          = 1,536 GiB
 
| max memory          = 1,536 GiB
  
−
| electrical          = Yes
+
 
 
| v core              = 1.82 V
 
| v core              = 1.82 V
 
| v core tolerance    =  
 
| v core tolerance    =  
Line 84: Line 103:
 
}}
 
}}
 
The '''Xeon E5-2698 v4''' is a {{arch|64}} [[icosa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for segment-optimized 2S environments (1U Square form factors). Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 3.6 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 
The '''Xeon E5-2698 v4''' is a {{arch|64}} [[icosa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for segment-optimized 2S environments (1U Square form factors). Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 3.6 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
 +
{{cache info
 +
|l1i cache=640 KiB
 +
|l1i break=20x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1i extra=(per core, write-back)
 +
|l1d cache=640 KiB
 +
|l1d break=20x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d extra=(per core, write-back)
 +
|l2 cache=5 MiB
 +
|l2 break=20x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 extra=(per core, write-back)
 +
|l3 cache=50 MiB
 +
|l3 break=20x2.5 MiB
 +
|l3 desc=20-way set associative
 +
|l3 extra=(shared, per core, write-back)
 +
}}
 +
 +
== Graphics ==
 +
This microprocessor has no [[integrated graphics processing unit]].
 +
 +
== Memory controller ==
 +
{{integrated memory controller
 +
| type              = DDR4-2400
 +
| controllers        = 1
 +
| channels          = 4
 +
| ecc support        = Yes
 +
| max bandwidth      = 71.53 GiB/s
 +
| bandwidth schan    = 17.88 GiB/s
 +
| bandwidth dchan    = 35.76 GiB/s
 +
| max memory        = 1,536 GiB
 +
| pae                = 46 bit
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 40
 +
| pcie config        = x4
 +
| pcie config 1      = x8
 +
| pcie config 2      = x16
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
| em64t      = Yes
 +
| nx          = Yes
 +
| txt        = Yes
 +
| tsx        = Yes
 +
| vpro        = Yes
 +
| ht          = Yes
 +
| tbt1        =
 +
| tbt2        = Yes
 +
| tbmt3      =
 +
| bpt        =
 +
| vt-x        = Yes
 +
| vt-d        = Yes
 +
| ept        = Yes
 +
| mmx        = Yes
 +
| sse        = Yes
 +
| sse2        = Yes
 +
| sse3        = Yes
 +
| ssse3      = Yes
 +
| sse4.1      = Yes
 +
| sse4.2      = Yes
 +
| aes        = Yes
 +
| pclmul      = Yes
 +
| avx        = Yes
 +
| avx2        = Yes
 +
| bmi        = Yes
 +
| bmi1        = Yes
 +
| bmi2        = Yes
 +
| f16c        = Yes
 +
| fma3        = Yes
 +
| mpx        =
 +
| sgx        =
 +
| eist        = Yes
 +
| secure key  = Yes
 +
| os guard    = Yes
 +
| intel at    =
 +
| intel ipt  =
 +
}}
 +
 +
== Benchmarks ==
 +
{{benchmarks main
 +
|
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q2/cpu2017-20161026-00026.html|test_timestamp=2016-12-09 16:58:22-0500|chip_count=2|core_count=40|copies_count=80|vendor=Inspur Corporation|system=Inspur NF5280M4 (Intel Xeon E5-2698 v4)|SPECrate2017_int_base=143|SPECrate2017_int_peak=148}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q2/cpu2017-20161026-00027.html|test_timestamp=2016-12-10 07:16:04-0500|chip_count=2|core_count=40|copies_count=80|vendor=Inspur Corporation|system=Inspur NF5280M4 (Intel Xeon E5-2698 v4)|SPECrate2017_fp_base=133|SPECrate2017_fp_peak=133}}
 +
}}

Latest revision as of 16:28, 13 December 2017

Edit Values
Xeon E5-2698 v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-2698 v4
Part NumberCM8066002024000
S-SpecSR2JW
QK11 (QS), QK7M (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
Release Price$3226.00
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-2000
LockedYes
Frequency2,200 MHz
Turbo FrequencyYes
Turbo Frequency3,600 MHz (1 core),
3,600 MHz (2 cores),
3,400 MHz (3 cores),
3,300 MHz (4 cores),
3,200 MHz (5 cores),
3,100 MHz (6 cores),
3,000 MHz (7 cores),
2,900 MHz (8 cores),
2,800 MHz (9 cores),
2,700 MHz (10 cores),
2,700 MHz (11 cores),
2,700 MHz (12 cores),
2,700 MHz (13 cores),
2,700 MHz (14 cores),
2,700 MHz (15 cores),
2,700 MHz (16 cores),
2,700 MHz (17 cores),
2,700 MHz (18 cores),
2,700 MHz (19 cores),
2,700 MHz (20 cores)
Bus typeQPI
Bus speed4,800 MHz
Bus rate2 × 9.6 GT/s
Clock multiplier22
CPUID406F1
Microarchitecture
MicroarchitectureBroadwell
PlatformGrantley EP 2S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingB0
Process14 nm
Transistors7,200,000,000
TechnologyCMOS
Die456.12 mm²
Word Size64 bit
Cores20
Threads40
Max Memory1,536 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP135 W
Tcase0 °C – 90 °C
Tstorage-25 °C – 125 °C

The Xeon E5-2698 v4 is a 64-bit icosa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for segment-optimized 2S environments (1U Square form factors). Operating at 2.2 GHz with a turbo boost frequency of 3.6 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 640 KiB
655,360 B
0.625 MiB
20x32 KiB 8-way set associative (per core, write-back)
L1D$ 640 KiB
655,360 B
0.625 MiB
20x32 KiB 8-way set associative (per core, write-back)
L2$ 5 MiB
5,120 KiB
5,242,880 B
0.00488 GiB
20x256 KiB 8-way set associative (per core, write-back)
L3$ 50 MiB
51,200 KiB
52,428,800 B
0.0488 GiB
20x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

Benchmarks[edit]

[Edit Benchmarks]

Test: SPEC CPU2017
Tested: 2016-12-09 16:58:22-0500
Chips: 2, Cores: 40, Copies: 80
benchmarks.svg
Vendor: Inspur Corporation
System: Inspur NF5280M4 (Intel Xeon E5-2698 v4)
SPECrate2017_int_base: 143
SPECrate2017_int_peak: 148
Test: SPEC CPU2017
Tested: 2016-12-10 07:16:04-0500
Chips: 2, Cores: 40, Copies: 80
benchmarks.svg
Vendor: Inspur Corporation
System: Inspur NF5280M4 (Intel Xeon E5-2698 v4)
SPECrate2017_fp_base: 133
SPECrate2017_fp_peak: 133
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2698_v4&oldid=71011"
Facts about "Xeon E5-2698 v4 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size640 KiB (655,360 B, 0.625 MiB) +
l1i$ description8-way set associative +
l1i$ size640 KiB (655,360 B, 0.625 MiB) +
l2$ description8-way set associative +
l2$ size5 MiB (5,120 KiB, 5,242,880 B, 0.00488 GiB) +
l3$ description20-way set associative +
l3$ size50 MiB (51,200 KiB, 52,428,800 B, 0.0488 GiB) +