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{{intel title|Xeon E5-4650 v4}}
 
{{intel title|Xeon E5-4650 v4}}
{{mpu
+
{{chip
 
| name                = Xeon E5-4650 v4
 
| name                = Xeon E5-4650 v4
 
| no image            = Yes
 
| no image            = Yes
Line 10: Line 10:
 
| model number        = E5-4650 v4
 
| model number        = E5-4650 v4
 
| part number        = CM8066002028621
 
| part number        = CM8066002028621
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Server
 
| market              = Server
 
| first announced    = June 20, 2016
 
| first announced    = June 20, 2016
Line 34: Line 34:
 
| s-spec              = SR2SA
 
| s-spec              = SR2SA
 
| s-spec es          =  
 
| s-spec es          =  
| s-spec qs          =  
+
| s-spec qs          = QKSQ
 
| cpuid              = 406F1
 
| cpuid              = 406F1
  
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| max memory          = 1,536 GiB
 
| max memory          = 1,536 GiB
  
| electrical          = Yes
+
 
 
| v core              = 1.82 V
 
| v core              = 1.82 V
 
| v core tolerance    =  
 
| v core tolerance    =  
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}}
 
}}
 
The '''Xeon E5-4650 v4''' is a {{arch|64}} [[tetradeca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for advanced 4S environments. Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 2.8 GHz for a single active core, this MPU has a TDP of 105 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 
The '''Xeon E5-4650 v4''' is a {{arch|64}} [[tetradeca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for advanced 4S environments. Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 2.8 GHz for a single active core, this MPU has a TDP of 105 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
 +
{{cache info
 +
|l1i cache=448 KiB
 +
|l1i break=14x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1i extra=(per core, write-back)
 +
|l1d cache=448 KiB
 +
|l1d break=14x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d extra=(per core, write-back)
 +
|l2 cache=3.5 MiB
 +
|l2 break=14x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 extra=(per core, write-back)
 +
|l3 cache=35 MiB
 +
|l3 break=14x2.5 MiB
 +
|l3 desc=20-way set associative
 +
|l3 extra=(shared, per core, write-back)
 +
}}
 +
 +
== Graphics ==
 +
This microprocessor has no [[integrated graphics processing unit]].
 +
 +
== Memory controller ==
 +
{{integrated memory controller
 +
| type              = DDR4-2133
 +
| controllers        = 1
 +
| channels          = 4
 +
| ecc support        = Yes
 +
| max bandwidth      = 63.58 GiB/s
 +
| bandwidth schan    = 15.89 GiB/s
 +
| bandwidth dchan    = 31.79 GiB/s
 +
| max memory        = 1,536 GiB
 +
| pae                = 46 bit
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 40
 +
| pcie config        = x4
 +
| pcie config 1      = x8
 +
| pcie config 2      = x16
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
| em64t      = Yes
 +
| nx          = Yes
 +
| txt        = Yes
 +
| tsx        = Yes
 +
| vpro        =
 +
| ht          = Yes
 +
| tbt1        =
 +
| tbt2        = Yes
 +
| tbmt3      =
 +
| bpt        =
 +
| vt-x        = Yes
 +
| vt-d        = Yes
 +
| ept        = Yes
 +
| mmx        = Yes
 +
| sse        = Yes
 +
| sse2        = Yes
 +
| sse3        = Yes
 +
| ssse3      = Yes
 +
| sse4.1      = Yes
 +
| sse4.2      = Yes
 +
| aes        = Yes
 +
| pclmul      = Yes
 +
| avx        = Yes
 +
| avx2        = Yes
 +
| bmi        = Yes
 +
| bmi1        = Yes
 +
| bmi2        = Yes
 +
| f16c        = Yes
 +
| fma3        = Yes
 +
| mpx        =
 +
| sgx        =
 +
| eist        = Yes
 +
| secure key  = Yes
 +
| os guard    = Yes
 +
| intel at    =
 +
| intel ipt  =
 +
}}

Latest revision as of 15:28, 13 December 2017

Edit Values
Xeon E5-4650 v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-4650 v4
Part NumberCM8066002028621
S-SpecSR2SA
QKSQ (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
Release Price$3838
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-4000
LockedYes
Frequency2,200 MHz
Turbo FrequencyYes
Turbo Frequency2,800 MHz (1 core)
Bus typeQPI
Bus speed4,800 MHz
Bus rate2 × 9.6 GT/s
Clock multiplier22
CPUID406F1
Microarchitecture
MicroarchitectureBroadwell
PlatformGrantley EP 4S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingM0
Process14 nm
Transistors4,700,000,000
TechnologyCMOS
Die306.18 mm²
Word Size64 bit
Cores14
Threads28
Max Memory1,536 GiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP105 W
Tcase0 °C – 80 °C
Tstorage-25 °C – 125 °C

The Xeon E5-4650 v4 is a 64-bit tetradeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for advanced 4S environments. Operating at 2.2 GHz with a turbo boost frequency of 2.8 GHz for a single active core, this MPU has a TDP of 105 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 448 KiB
458,752 B
0.438 MiB
14x32 KiB 8-way set associative (per core, write-back)
L1D$ 448 KiB
458,752 B
0.438 MiB
14x32 KiB 8-way set associative (per core, write-back)
L2$ 3.5 MiB
3,584 KiB
3,670,016 B
0.00342 GiB
14x256 KiB 8-way set associative (per core, write-back)
L3$ 35 MiB
35,840 KiB
36,700,160 B
0.0342 GiB
14x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2133
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 63.58 GiB/s
Bandwidth (single) 15.89 GiB/s
Bandwidth (dual) 31.79 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-4650 v4 - Intel#io +
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus links2 +
bus rate9,600 MT/s (9.6 GT/s, 9,600,000 kT/s) +
bus speed4,800 MHz (4.8 GHz, 4,800,000 kHz) +
bus typeQPI +
chipsetC610 Series +
clock multiplier22 +
core count14 +
core family6 +
core model4F +
core nameBroadwell EP +
core steppingM0 +
core voltage1.82 V (18.2 dV, 182 cV, 1,820 mV) +
cpuid406F1 +
designerIntel +
die area306.18 mm² (0.475 in², 3.062 cm², 306,180,000 µm²) +
familyXeon E5 +
first announcedJune 20, 2016 +
first launchedJune 20, 2016 +
full page nameintel/xeon e5/e5-4650 v4 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
io voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
io voltage tolerance3% +
l1d$ description8-way set associative +
l1d$ size448 KiB (458,752 B, 0.438 MiB) +
l1i$ description8-way set associative +
l1i$ size448 KiB (458,752 B, 0.438 MiB) +
l2$ description8-way set associative +
l2$ size3.5 MiB (3,584 KiB, 3,670,016 B, 0.00342 GiB) +
l3$ description20-way set associative +
l3$ size35 MiB (35,840 KiB, 36,700,160 B, 0.0342 GiB) +
ldateJune 20, 2016 +
manufacturerIntel +
market segmentServer +
max case temperature353.15 K (80 °C, 176 °F, 635.67 °R) +
max cpu count4 +
max memory1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) +
max pcie lanes40 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureBroadwell +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberE5-4650 v4 +
nameXeon E5-4650 v4 +
part numberCM8066002028621 +
platformGrantley EP 4S +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 3,838.00 (€ 3,454.20, £ 3,108.78, ¥ 396,580.54) +
s-specSR2SA +
s-spec (qs)QKSQ +
seriesE5-4000 +
smp max ways4 +
tdp105 W (105,000 mW, 0.141 hp, 0.105 kW) +
technologyCMOS +
thread count28 +
transistor count4,700,000,000 +
turbo frequency (1 core)2,800 MHz (2.8 GHz, 2,800,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +