Latest revision as of 15:28, 13 December 2017

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Xeon E7-4860
General Info
Designer	Intel
Manufacturer	Intel
Model Number	E7-4860
Part Number	AT80615007254AA
S-Spec	SLC3S
Market	Server
Introduction	April 5, 2011 (announced) April 5, 2011 (launched)
End-of-life	August 21, 2015 (last order) February 5, 2016 (last shipment)
Release Price	$3838.00
Shop	Amazon
General Specs
Family	Xeon E7
Series	E7-4800
Locked	Yes
Frequency	2,266.66 MHz
Turbo Frequency	Yes
Turbo Frequency	2,666.66 MHz (1 core), 2,666.66 MHz (2 cores), 2,666.66 MHz (3 cores), 2,666.66 MHz (4 cores), 2,533.33 MHz (5 cores), 2,533.33 MHz (6 cores), 2,399.99 MHz (7 cores), 2,399.99 MHz (8 cores), 2,399.99 MHz (9 cores), 2,399.99 MHz (10 cores)
Bus type	QPI
Bus rate	6.40 GT/s
Clock multiplier	17
CPUID	206F2
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Westmere
Platform	Boxboro
Chipset	Boxboro
Core Name	Westmere EX
Core Family	6
Core Model	47
Core Stepping	A2
Process	32 nm
Transistors	2,600,000,000
Technology	CMOS
Die	513 mm²
Word Size	64 bit
Cores	10
Threads	20
Max Memory	2 TiB
Multiprocessing
Max SMP	4-Way (Multiprocessor)
Electrical
Vcore	1.35 V
TDP	130 W
Tcase	5 °C – 69 °C
Tstorage	-40 °C – 85 °C
Packaging
Package FCLGA-8 (LGA) Dimension 49.1 mm x 56.4 mm x 4.2 mm Pitch 1 mm Pin Count 1567 Socket LGA-1567

Xeon E7-4860 is a 64-bit deca-core x86 data center microprocessor that supports up to 4 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2.26 GHz with turbo frequency of 2.66 GHz for 2 active cores. This chip has a TDP of 130 W, supporting up to 4 channels of DDR3 with support of up to 2 TB of memory.

Cache[edit]

Main article: Westmere § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 640 KiB 655,360 B 0.625 MiB L1I$ 320 KiB 327,680 B 0.313 MiB 10x32 KiB 4-way set associative write-back L1D$ 320 KiB 327,680 B 0.313 MiB 10x32 KiB 8-way set associative write-back L2$ 2.56 MiB 2,621.44 KiB 2,684,354.56 B 0.0025 GiB     10x256 KiB 8-way set associative write-back L3$ 24 MiB 24,576 KiB 25,165,824 B 0.0234 GiB     10x2.4 MiB 16-way set associative write-back

Graphics[edit]

This SoC has no integrated graphics processing unit.

Memory controller[edit]

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1066 Supports ECC Yes Max Mem 2 TiB Controllers 1 Channels 4 Max Bandwidth 31.77 GiB/s 32,532.48 MiB/s 34.113 GB/s 34,112.778 MB/s 0.031 TiB/s 0.0341 TB/s Bandwidth Single 7.942 GiB/s Double 15.88 GiB/s Triple 23.83 GiB/s Quad 31.77 GiB/s Physical Address (PAE) 44 bit

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AES AES Encryption Instructions x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 1.0 Turbo Boost Technology 1.0 EIST Enhanced SpeedStep Technology TXT Trusted Execution Technology (SMX) VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT)

Die Shot[edit]

• 513 mm²
• 2,600,000,000 transistors
• 10 cores