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Difference between revisions of "pezy/pezy-1"
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(Created page with "{{pezy title|PEZY-1}} {{mpu | name = PEZY-1 | no image = Yes | image = | image size = | caption = | designer...")
 
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{{pezy title|PEZY-1}}
 
{{pezy title|PEZY-1}}
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{{mpu
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{{chip
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| name               = PEZY-1
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|name=PEZY-1
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| no image           = Yes
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|image=pezy 1.jpg
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| image              =
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|designer=PEZY
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| image size          =
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|manufacturer=TSMC
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| caption            =  
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|model number=PEZY-1
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| designer           = PEZY
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|market=Industrial
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| manufacturer       = TSMC
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|first announced=2011
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| model number       = PEZY-1
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|first launched=2012
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| part number        =
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|frequency=533.33 MHz
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| market             = Industrial
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|process=40 nm
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| first announced     = 2011
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|technology=CMOS
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| first launched     = 2012
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|die area=335 mm²
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| last order          =  
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|die length=16.8 mm
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| last shipment      =  
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|die width=21 mm
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|core count=512
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|power=35 W
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|tjunc min=<!-- °C -->
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|electrical=Yes
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|packaging=Yes
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|package 0=fcBGA-1517
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|package 0 type=fcBGA
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|package 0 pins=1517
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|package 0 pitch=1 mm
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|package 0 width=40 mm
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|package 0 length=40 mm
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|package 0 height=3.01 mm
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|socket 0=BGA-1517
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|socket 0 type=BGA
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}}
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'''PEZY-1''' was a first generation [[many-core microprocessor]] developed by [[PEZY]] in 2012. PEZY-1 contains 2 {{armh|ARM926}} cores ({{arm|ARMv5TEJ}}) along with 512 simpler RISC cores. Operating at 533 MHz, the processor is said to have peak performance of 533 GFLOPS (single-precision) and 266 GFLOPS (double-precision). PEZY-1 was designed using 220 million gates and manufactured on TSMC's [[40 nm process]].
  
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| family              =
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The PEZY-1 is used for image processing devices and various medical instruments. In 2014 PEZY introduced their second generation many-core processor, the {{pezy|PEZY-SC}}, with twice as many cores and formed the basis for the {{pezy|PEZY-SCx}} family.
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| series              =
 
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| locked              =
 
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| frequency          = 533.33 MHz
 
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| bus type            =
 
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| bus speed          = 66.66 MHz
 
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| bus rate            =
 
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| clock multiplier    = 8
 
  
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| microarch          =  
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== Cache ==
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| platform            =  
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PEZY-1's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of 16 KiB (2x) and no L2$.
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| chipset            =  
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{{cache size
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| core name          =  
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|l1 cache=128 KiB
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| core family        =
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|l1i cache=64 KiB
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| core model          =
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|l1i break=1x64 KiB
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| core stepping      =  
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|l1d cache=64 KiB
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| process            = 40 nm
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|l1d break=1x64 KiB
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| transistors        =  
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|l2 cache=1 MiB
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| technology          = CMOS
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|l2 break=1x1 MiB
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| die area            = 335 mm²
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}}
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| die width          = 21 mm
 
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| die length          = 16.8 mm
 
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| word size          =
 
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| core count          = 512
 
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| thread count        =
 
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| max cpus            =
 
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| max memory          =
 
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| max memory addr    =
 
  
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| electrical          = Yes
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== Memory controller ==
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| power              = 35 W
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{{memory controller
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| v core              =
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|type=DDR3-1333
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| v core tolerance    =  
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|ecc=Yes
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| v io                =  
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|controllers=4
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| v io tolerance      =  
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|channels=4
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| sdp                =
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|width=64 bit
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| tdp                =  
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|max bandwidth=39.74 GiB/s
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| ctdp down          =
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|bandwidth schan=9.93 GiB/s
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| ctdp down frequency =
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|bandwidth dchan=19.86 GiB/s
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| ctdp up            =
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|bandwidth qchan=39.74 GiB/
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| ctdp up frequency  =  
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}}
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| temp min            =  
 
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| temp max            =  
 
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| tjunc min          = <!-- °C -->
 
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| tjunc max           =  
 
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| tcase min          =  
 
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| tcase max          =  
 
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| tstorage min        =  
 
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| tstorage max        =
 
  
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| packaging          = Yes
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== Expansions ==
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| package 0          = fcBGA-1517
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{{expansions
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| package 0 type      = fcBGA
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| pcie revision     = 2.0
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| package 0 pins     = 1517
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| pcie lanes        = 24
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| package 0 pitch    = 1 mm
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| pcie config        = 6x4
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| package 0 width    = 40 mm
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| uart              = Yes
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| package 0 length    = 40 mm
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| gp io              = Yes
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| package 0 height    = 3.01 mm
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}}
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| socket 0            = BGA-1517
 
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| socket 0 type      = BGA}}
 
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'''PEZY-1''' was a first generation [[many-core microprocessor]] developed by [[PEZY]] in 2012. PEZY-1 contains 2 {{armh|ARM926}} cores ({{arm|ARMv5TEJ}}) along with 512 simpler RISC cores. Operating at 533 MHz, the processor is said to have peach performance of 533 GFLOPS (single-precision) and 266 GFLOPS (double-precision). PEZY-1 was designed using 220 million gates and manufactured on TSMC's [[40 nm process]].
 
  
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The PEZY-1 is used for image processing devices and various medical instruments.
+
== PEZY-1 Quad PCI Board ==
 +
[[File:pezy 1 quad pci board.jpg|200px|right]]
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PEZY has developed a Quad-PEZY-1 PCI board for their microprocessors which has 4 PEZY-1 for a total of 2,048 PE cores (along with 8 ARM cores). The board is equipped with 64 GiB of memory for a total bandwidth of 200 GB/s. PEZY reports the total computational power for the board to be at 2.56 TFLOPS with a power consumption of 180 Watts.
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== Documents ==
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* [[:File:pezy 1 board.pdf|PEZY-1 Board]]
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* [[:File:PEZY Computing (February 20, 2015).pdf|PEZY Computing (February 20, 2015)]]

Latest revision as of 03:48, 20 October 2018

Edit Values
PEZY-1
pezy 1.jpg
General Info
DesignerPEZY
ManufacturerTSMC
Model NumberPEZY-1
MarketIndustrial
Introduction2011 (announced)
2012 (launched)
General Specs
Frequency533.33 MHz
Microarchitecture
Process40 nm
TechnologyCMOS
Die335 mm²
16.8 mm × 21 mm
Cores512
Electrical
Power dissipation35 W

PEZY-1 was a first generation many-core microprocessor developed by PEZY in 2012. PEZY-1 contains 2 ARM926 cores (ARMv5TEJ) along with 512 simpler RISC cores. Operating at 533 MHz, the processor is said to have peak performance of 533 GFLOPS (single-precision) and 266 GFLOPS (double-precision). PEZY-1 was designed using 220 million gates and manufactured on TSMC's 40 nm process.

The PEZY-1 is used for image processing devices and various medical instruments. In 2014 PEZY introduced their second generation many-core processor, the PEZY-SC, with twice as many cores and formed the basis for the PEZY-SCx family.

Cache[edit]

PEZY-1's cache is separate from the ARM926's cache which has an L1$ of 16 KiB (2x) and no L2$.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB  
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB  
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  1x1 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1333
Supports ECCYes
Controllers4
Channels4
Width64 bit
Max Bandwidth39.74 GiB/s
40,693.76 MiB/s
42.671 GB/s
42,670.5 MB/s
0.0388 TiB/s
0.0427 TB/s
Bandwidth
Single 9.93 GiB/s
Double 19.86 GiB/s
Quad 39.74 GiB/

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes24
Configs6x4
UART
GP I/OYes


PEZY-1 Quad PCI Board[edit]

pezy 1 quad pci board.jpg

PEZY has developed a Quad-PEZY-1 PCI board for their microprocessors which has 4 PEZY-1 for a total of 2,048 PE cores (along with 8 ARM cores). The board is equipped with 64 GiB of memory for a total bandwidth of 200 GB/s. PEZY reports the total computational power for the board to be at 2.56 TFLOPS with a power consumption of 180 Watts.

Documents[edit]

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