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Difference between revisions of "intel/celeron/n3350"
< intel‎ | celeron

(temp)
(Added missing features, as per https://valid.x86.fr/mrj60f and my own lscpu run)
 
(10 intermediate revisions by 3 users not shown)
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{{intel title|Celeron N3350}}
 
{{intel title|Celeron N3350}}
−
{{mpu
+
{{chip
 
| name                = Celeron N3350
 
| name                = Celeron N3350
 
| no image            = Yes
 
| no image            = Yes
Line 7: Line 7:
 
| model number        = N3350
 
| model number        = N3350
 
| part number        = FH8066802980002
 
| part number        = FH8066802980002
−
| part number 1       = FH8066802980002
+
| part number 2       = FH8066802980002
−
| part number 2      =
 
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Mobile
 
| market              = Mobile
 
| first announced    = August 30, 2016
 
| first announced    = August 30, 2016
Line 15: Line 15:
 
| last order          =  
 
| last order          =  
 
| last shipment      =  
 
| last shipment      =  
 +
| release price      = $107.00
  
 
| family              = Celeron
 
| family              = Celeron
Line 32: Line 33:
 
| cpuid              =  
 
| cpuid              =  
  
 +
| isa family          = x86
 +
| isa                = x86-64
 
| microarch          = Goldmont
 
| microarch          = Goldmont
 
| platform            =  
 
| platform            =  
Line 45: Line 48:
 
| thread count        = 2
 
| thread count        = 2
 
| max cpus            = 1
 
| max cpus            = 1
−
| max memory          = 8 GB
+
| max memory          = 8 GiB
 +
 
  
−
| electrical          = Yes
 
 
| power              =  
 
| power              =  
 
| v core              =  
 
| v core              =  
Line 80: Line 83:
  
 
== Cache ==
 
== Cache ==
−
{{main|intel/microarchitectures/goldmont#Memory_Hierarchy|l1=Goldmont's Cache}}
+
{{main|intel/microarchitectures/goldmont#Memory_Hierarchy|l1=Goldmont § Cache}}
 
{{cache info
 
{{cache info
−
|l1i cache=64 KB
+
|l1i cache=64 KiB
−
|l1i break=2x32 KB
+
|l1i break=2x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
 
|l1i extra=(per core)
 
|l1i extra=(per core)
−
|l1d cache=48 KB
+
|l1d cache=48 KiB
−
|l1d break=4x24 KB
+
|l1d break=4x24 KiB
 
|l1d desc=6-way set associative
 
|l1d desc=6-way set associative
 
|l1d extra=(per core)
 
|l1d extra=(per core)
−
|l2 cache=1 MB
+
|l2 cache=1 MiB
−
|l2 break=1x1 MB
+
|l2 break=1x1 MiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 extra=(per 2 cores)
 
|l2 extra=(per 2 cores)
−
|l3 cache=0 KB
+
|l3 cache=0 KiB
 
|l3 desc=No L3$
 
|l3 desc=No L3$
 
}}
 
}}
Line 125: Line 128:
 
| frequency          = 200 MHz
 
| frequency          = 200 MHz
 
| max frequency      = 650 MHz
 
| max frequency      = 650 MHz
−
| max memory          = 8 GB
+
| max memory          = 8 GiB
  
 
| output crt          =  
 
| output crt          =  
Line 172: Line 175:
  
 
== Expansions ==
 
== Expansions ==
−
{{mpu expansions
+
{{expansions
 
| pcie revision      = 2.0
 
| pcie revision      = 2.0
 
| pcie lanes        = 6
 
| pcie lanes        = 6
Line 196: Line 199:
  
 
== Features ==  
 
== Features ==  
−
{{mpu features
+
{{x86 features
−
| em64t      = Yes
+
|real=No
−
| nx          = Yes
+
|protected=No
−
| txt        = Yes
+
|smm=No
−
| tsx        =  
+
|fpu=No
−
| vpro        =  
+
|x8616=No
−
| ht          =  
+
|x8632=No
−
| tbt1        =
+
|x8664=No
−
| tbt2        =  
+
|nx=Yes
−
| bpt        = Yes
+
|mmx=Yes
−
| vt-x        = Yes
+
|emmx=No
−
| vt-d        = Yes
+
|sse=Yes
−
| ept        = Yes
+
|sse2=Yes
−
| mmx        = Yes
+
|sse3=Yes
−
| sse        = Yes
+
|ssse3=Yes
−
| sse2        = Yes
+
|sse41=Yes
−
| sse3        = Yes
+
|sse42=Yes
−
| ssse3      = Yes
+
|sse4a=No
−
| sse4.1      = Yes
+
|sse_gfni=No
−
| sse4.2      = Yes
+
|avx=No
−
| aes        = Yes
+
|avx_gfni=No
−
| pclmul      = Yes
+
|avx2=No
−
| avx        =  
+
|avx512f=No
−
| avx2        =  
+
|avx512cd=No
−
| bmi        =  
+
|avx512er=No
−
| bmi1        =  
+
|avx512pf=No
−
| bmi2        =  
+
|avx512bw=No
−
| f16c        =  
+
|avx512dq=No
−
| fma3        =  
+
|avx512vl=No
−
| mpx        =  
+
|avx512ifma=No
−
| sgx        =  
+
|avx512vbmi=No
−
| eist        = Yes
+
|avx5124fmaps=No
−
| secure key  = Yes
+
|avx512vnni=No
−
| os guard    =  
+
|avx5124vnniw=No
−
| intel at    =  
+
|avx512vpopcntdq=No
 +
|avx512gfni=No
 +
|avx512vaes=No
 +
|avx512vbmi2=No
 +
|avx512bitalg=No
 +
|avx512vpclmulqdq=No
 +
|abm=No
 +
|tbm=No
 +
|bmi1=No
 +
|bmi2=No
 +
|fma3=No
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=No
 +
|sha=Yes
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=No
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|tvb=No
 +
|bpt=Yes
 +
|eist=Yes
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|tme=No
 +
|mktme=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=Yes
 +
|ht=No
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=No
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|dlboost=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
|em64t=Yes
 +
|vt-x=Yes
 +
|vt-d=Yes
 +
|sse4_1=Yes
 +
|sse4_2=Yes
 +
|pclmul=Yes
 +
|secure key=Yes
 
}}
 
}}

Latest revision as of 19:58, 21 October 2023

Edit Values
Celeron N3350
General Info
DesignerIntel
ManufacturerIntel
Model NumberN3350
Part NumberFH8066802980002,
FH8066802980002
S-SpecSR2YB, SR2Z7
MarketMobile
IntroductionAugust 30, 2016 (announced)
August 30, 2016 (launched)
Release Price$107.00
ShopAmazon
General Specs
FamilyCeleron
SeriesN Series
LockedYes
Frequency1100 MHz
Turbo FrequencyYes
Turbo Frequency2400 MHz (1 core)
Clock multiplier11
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureGoldmont
Core NameApollo Lake
Core SteppingB0, B1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores2
Threads2
Max Memory8 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
SDP4 W
TDP6 W
Tjunction0 °C – 105 °C
Tstorage-25 °C – 125 °C

Celeron N3350 is a dual-core 64-bit x86 mobile microprocessor introduced by Intel in 2016. The processor is based on Goldmont microarchitecture and is manufactured on a 14 nm process. The chip operates at 1.1 GHz with burst frequency of 2.4 GHz and has a TDP of 6 W (SDP of 4 W). This MPU incorporates Intel's HD Graphics 500 GPU operating at 200 MHz with a burst frequency of 650 MHz.

Cache[edit]

Main article: Goldmont § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core)
L1D$ 48 KiB
49,152 B
0.0469 MiB
4x24 KiB 6-way set associative (per core)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
1x1 MiB 16-way set associative (per 2 cores)
L3$ 0 KiB
0 MiB
0 B
0 GiB
No L3$

Memory controller[edit]

Integrated Memory Controller
Type LPDDR3-1333, LPDDR3-1600, LPDDR3-2400, DDR3L-1333, DDR3L-1600, DDR3L-1867, LPDDR4-1600, LPDDR4-2133, LPDDR4-2400
Controllers 1
Channels 2
ECC Support No
Bandwidth (single) 19,200 MB/s
Bandwidth (dual) 38,400 MB/s
Max memory 8,192 MB

Graphics[edit]

Integrated Graphic Information
GPU HD Graphics 500
Device ID 0x5A85
Execution Units 12
Displays 3
Frequency 200 MHz
0.2 GHz
200,000 KHz
Max frequency 650 MHz
0.65 GHz
650,000 KHz
Max memory 8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
Output DisplayPort, Embedded DisplayPort, HDMI, DSI
DirectX 12
OpenGL 4.3
OpenCL 1.2
OpenGL ES 3.0
HDMI 1.4b
DP 1.2
eDP 1.3
Max HDMI Res 3840x2160 @30 Hz
Max DSI Res 2560x1600 @60 Hz
Max DP Res 4096x2160 @60 Hz
Max eDP Res 3840x2160 @60 Hz
Intel Quick Sync Video
Intel Clear Video
  • Video decode hardware acceleration including support for HEVC (H.265), H.264, MVC, VP8, VP9, MPEG2, VC-1, WMV9, JPEG/MJPEG.
  • Video encode hardware acceleration including support for HEVC (H.265), H.264, MVC, VP8, VP9, JPEG/MJPEG.

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes6
Configs4x1, 2x1 + 1x2 + 1x2
USB
Revision2.0, 3.0
Ports8
UART
SATA
Revision3.0
Ports3
GP I/OYes


  • 2x USB 2.0 ports
  • 6x USB 3.0 ports
    • 1x USB Dual Role
    • 1x Dedicated Port
    • 3x multiplexed with PCIe 2.0
    • 1x multiplexed with SATA 3.0

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AESAES Encryption Instructions
SHASHA Extensions
NXNo-eXecute
BPTBurst Performance Technology
EISTEnhanced SpeedStep Technology
TXTTrusted Execution Technology (SMX)
VT-xVT-x (Virtualization)
EPTExtended Page Tables (SLAT)
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/n3350&oldid=101950"
Facts about "Celeron N3350 - Intel"
RDF feed
device id0x5A85 +
has featureintegrated gpu +
integrated gpuHD Graphics 500 +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu max frequency650 MHz (0.65 GHz, 650,000 KHz) +
l1d$ description6-way set associative +
l1i$ description8-way set associative +
l2$ description16-way set associative +
l3$ descriptionNo L3$ +