Semiconductor & Computer Engineering
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Difference between revisions of "amd/duron/dm600avs1b"
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| − | {{amd title|Duron 600 (Spitfire | + | {{amd title|Mobile Duron 600 (Spitfire)}} |
| − | {{ | + | {{chip |
| name = Duron 600 | | name = Duron 600 | ||
| no image = Yes | | no image = Yes | ||
| Line 10: | Line 10: | ||
| model number = Duron 600 | | model number = Duron 600 | ||
| part number = DM600AVS1B | | part number = DM600AVS1B | ||
| − | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Mobile | | market = Mobile | ||
| first announced = January 15, 2001 | | first announced = January 15, 2001 | ||
| Line 45: | Line 45: | ||
| thread count = 1 | | thread count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| + | |||
| − | |||
| power = | | power = | ||
| v core = 1.4 V | | v core = 1.4 V | ||
| Line 79: | Line 79: | ||
| socket 0 type = PGA-462 | | socket 0 type = PGA-462 | ||
}} | }} | ||
| + | '''Mobile Duron 600''' based on the {{amd|Spitfire|l=core}} core was a {{arch|32}} mobile [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in early 2001. This model was part of the first series of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} (a {{amd|Thunderbird}}-derivative) on a [[180 nm process]], this MPU operated at 600 MHz with a bus capable of 200 MT/s. | ||
| + | |||
| + | == Cache == | ||
| + | {{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | ||
| + | {{cache info | ||
| + | |l1i cache=64 KiB | ||
| + | |l1i break=1x64 KiB | ||
| + | |l1i desc=2-way set associative | ||
| + | |l1i extra= | ||
| + | |l1d cache=64 KiB | ||
| + | |l1d break=1x64 KiB | ||
| + | |l1d desc=2-way set associative | ||
| + | |l1d extra= | ||
| + | |l2 cache=64 KiB | ||
| + | |l2 break=1x64 KiB | ||
| + | |l2 desc=16-way set associative | ||
| + | |l2 extra= | ||
| + | |l3 cache= | ||
| + | |l3 break= | ||
| + | |l3 desc= | ||
| + | |l3 extra= | ||
| + | }} | ||
| + | |||
| + | == Graphics == | ||
| + | This SoC has no integrated graphics processing unit. | ||
| + | |||
| + | == Features == | ||
| + | {{x86 features | ||
| + | | em64t = | ||
| + | | nx = | ||
| + | | txt = | ||
| + | | tsx = | ||
| + | | vpro = | ||
| + | | ht = | ||
| + | | tbt1 = | ||
| + | | tbt2 = | ||
| + | | bpt = | ||
| + | | vt-x = | ||
| + | | vt-d = | ||
| + | | ept = | ||
| + | | mmx = Yes | ||
| + | | emmx = Yes | ||
| + | | 3dnow = Yes | ||
| + | | e3dnow = Yes | ||
| + | | sse = | ||
| + | | sse2 = | ||
| + | | sse3 = | ||
| + | | ssse3 = | ||
| + | | sse4 = | ||
| + | | sse4.1 = | ||
| + | | sse4.2 = | ||
| + | | aes = | ||
| + | | pclmul = | ||
| + | | avx = | ||
| + | | avx2 = | ||
| + | | bmi = | ||
| + | | bmi1 = | ||
| + | | bmi2 = | ||
| + | | f16c = | ||
| + | | fma3 = | ||
| + | | mpx = | ||
| + | | sgx = | ||
| + | | eist = | ||
| + | }} | ||
| + | * [[has feature::Halt State]] | ||
| + | * [[has feature::Sleep State]] | ||
Latest revision as of 15:07, 13 December 2017
| Edit Values | |
| Duron 600 | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | Duron 600 |
| Part Number | DM600AVS1B |
| Market | Mobile |
| Introduction | January 15, 2001 (announced) January 15, 2001 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | Duron |
| Series | Duron Mobile |
| Locked | Yes |
| Frequency | 600 MHz |
| Bus type | FSB |
| Bus speed | 100 MHz |
| Bus rate | 200 MT/s |
| Clock multiplier | 6 |
| CPUID | 630 |
| Microarchitecture | |
| Microarchitecture | K7 |
| Core Name | Spitfire |
| Core Family | 6 |
| Core Model | 3 |
| Core Stepping | 0 |
| Process | 180 nm |
| Transistors | 25,000,000 |
| Technology | CMOS |
| Die | 100 mm² |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Vcore | 1.4 V ± 0.1 V |
| Tcase | 0 °C – 95 °C |
| Tstorage | -40 °C – 100 °C |
Mobile Duron 600 based on the Spitfire core was a 32-bit mobile x86 microprocessor developed by AMD and introduced in early 2001. This model was part of the first series of the Duron family. Designed based on AMD's K7 (a Thunderbird-derivative) on a 180 nm process, this MPU operated at 600 MHz with a bus capable of 200 MT/s.
Cache[edit]
- Main article: K7 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L1D$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L2$ | 64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB |
1x64 KiB 16-way set associative |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
|
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- Halt State
- Sleep State
Facts about "Mobile Duron 600 (Spitfire) - AMD"
| has feature | Halt State + and Sleep State + |
| l1d$ description | 2-way set associative + |
| l1i$ description | 2-way set associative + |
| l2$ description | 16-way set associative + |