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Difference between revisions of "amd/duron/d650ast1b"
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{{amd title|Duron 650 (Spitfire)}} | {{amd title|Duron 650 (Spitfire)}} | ||
| − | {{ | + | {{chip |
| name = Duron 650 | | name = Duron 650 | ||
| no image = Yes | | no image = Yes | ||
| Line 10: | Line 10: | ||
| model number = Duron 650 | | model number = Duron 650 | ||
| part number = D650AST1B | | part number = D650AST1B | ||
| − | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Desktop | | market = Desktop | ||
| first announced = June 5, 2000 | | first announced = June 5, 2000 | ||
| Line 45: | Line 45: | ||
| thread count = 1 | | thread count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| + | |||
| − | |||
| power = | | power = | ||
| v core = 1.5 V | | v core = 1.5 V | ||
| Line 79: | Line 79: | ||
| socket 0 type = PGA-462 | | socket 0 type = PGA-462 | ||
}} | }} | ||
| − | '''Duron 650''' based on the Spitfire core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in 2000. This model was part of the first series of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} (a {{amd|Thunderbird}}-derivative) on a [[180 nm process]], this MPU operated at 650 MHz with a bus capable of 200 MT/s with a TDP of 24.3 W. | + | '''Duron 650''' based on the {{amd|Spitfire|l=core}} core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in 2000. This model was part of the first series of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} (a {{amd|Thunderbird}}-derivative) on a [[180 nm process]], this MPU operated at 650 MHz with a bus capable of 200 MT/s with a TDP of 24.3 W. |
== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | {{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1i cache=64 | + | |l1i cache=64 KiB |
| − | |l1i break=1x64 | + | |l1i break=1x64 KiB |
|l1i desc=2-way set associative | |l1i desc=2-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=64 | + | |l1d cache=64 KiB |
| − | |l1d break=1x64 | + | |l1d break=1x64 KiB |
|l1d desc=2-way set associative | |l1d desc=2-way set associative | ||
|l1d extra= | |l1d extra= | ||
| − | |l2 cache=64 | + | |l2 cache=64 KiB |
| − | |l2 break=1x64 | + | |l2 break=1x64 KiB |
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
|l2 extra= | |l2 extra= | ||
| Line 106: | Line 106: | ||
== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| em64t = | | em64t = | ||
| nx = | | nx = | ||
| Line 145: | Line 145: | ||
* [[has feature::Halt State]] | * [[has feature::Halt State]] | ||
* [[has feature::Sleep State]] | * [[has feature::Sleep State]] | ||
| + | |||
| + | == Documents == | ||
| + | === DataSheet === | ||
| + | * [[:File:AMD Duron Processor Model 3 Data Sheet (June, 2001).pdf|AMD Duron Processor Model 3 Data Sheet]]; Publication # 23802; Rev: I; Issue Date: June 2001. | ||
| + | === Other === | ||
| + | * [[:File:AMD Duron Processor Model 3 Revision Guide (October, 2003).pdf|AMD Duron Processor Model 3 Revision Guide]]; Publication # 23865; Rev: K; Issue Date: October 2003. | ||
Latest revision as of 15:07, 13 December 2017
| Edit Values | |
| Duron 650 | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | Duron 650 |
| Part Number | D650AST1B |
| Market | Desktop |
| Introduction | June 5, 2000 (announced) June 19, 2000 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | Duron |
| Series | Duron Desktop |
| Locked | Yes |
| Frequency | 650 MHz |
| Bus type | FSB |
| Bus speed | 100 MHz |
| Bus rate | 200 MT/s |
| Clock multiplier | 6.5 |
| CPUID | 630 |
| Microarchitecture | |
| Microarchitecture | K7 |
| Core Name | Spitfire |
| Core Family | 6 |
| Core Model | 3 |
| Core Stepping | 0 |
| Process | 180 nm |
| Transistors | 25,000,000 |
| Technology | CMOS |
| Die | 100 mm² |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Vcore | 1.5 V ± 0.1 V |
| TDP | 24.3 W |
| Tcase | 0 °C – 90 °C |
| Tstorage | -40 °C – 100 °C |
Duron 650 based on the Spitfire core was a 32-bit x86 microprocessor developed by AMD and introduced in 2000. This model was part of the first series of the Duron family. Designed based on AMD's K7 (a Thunderbird-derivative) on a 180 nm process, this MPU operated at 650 MHz with a bus capable of 200 MT/s with a TDP of 24.3 W.
Cache[edit]
- Main article: K7 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L1D$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L2$ | 64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB |
1x64 KiB 16-way set associative |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
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- Halt State
- Sleep State
Documents[edit]
DataSheet[edit]
- AMD Duron Processor Model 3 Data Sheet; Publication # 23802; Rev: I; Issue Date: June 2001.
Other[edit]
- AMD Duron Processor Model 3 Revision Guide; Publication # 23865; Rev: K; Issue Date: October 2003.
Facts about "Duron 650 (Spitfire) - AMD"
| has feature | Halt State + and Sleep State + |
| l1d$ description | 2-way set associative + |
| l1i$ description | 2-way set associative + |
| l2$ description | 16-way set associative + |