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Difference between revisions of "amd/duron/d600aut1b"
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{{amd title|Duron 600 (Spitfire)}}
 
{{amd title|Duron 600 (Spitfire)}}
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{{mpu
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{{chip
 
| name                = Duron 600
 
| name                = Duron 600
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| no image            = Yes
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| no image            =  
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| image              =  
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| image              = KL AMD Duron Spitfire.jpg
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| image size          =  
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| image size          = 250px
 
| caption            =  
 
| caption            =  
 
| designer            = AMD
 
| designer            = AMD
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| model number        = Duron 600
 
| model number        = Duron 600
 
| part number        = D600AUT1B
 
| part number        = D600AUT1B
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| part number 1       = D0600AUT1B
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| part number 2       = D0600AUT1B
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| part number 2      =
 
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Desktop
 
| market              = Desktop
 
| first announced    = June 5, 2000
 
| first announced    = June 5, 2000
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| thread count        = 1
 
| thread count        = 1
 
| max cpus            = 1
 
| max cpus            = 1
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| max memory          = 4 GB
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| max memory          = 4 GiB
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| electrical          = Yes
 
 
| power              =  
 
| power              =  
 
| v core              = 1.6 V
 
| v core              = 1.6 V
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| socket 0 type      = PGA-462
 
| socket 0 type      = PGA-462
 
}}
 
}}
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'''Duron 600''' based on the Spitfire core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in 2000. This model was part of the first series of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} (a {{amd|Thunderbird}}-derivative) on a [[180 nm process]], this MPU operated at 550 MHz with a bus capable of 200 MT/s with a typical TDP of 27.4 W.
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'''Duron 600''' based on the {{amd|Spitfire|l=core}} core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in 2000. This model was part of the first series of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} (a {{amd|Thunderbird}}-derivative) on a [[180 nm process]], this MPU operated at 550 MHz with a bus capable of 200 MT/s with a typical TDP of 27.4 W.
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== Cache ==
 +
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
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{{cache info
 +
|l1i cache=64 KiB
 +
|l1i break=1x64 KiB
 +
|l1i desc=2-way set associative
 +
|l1i extra=
 +
|l1d cache=64 KiB
 +
|l1d break=1x64 KiB
 +
|l1d desc=2-way set associative
 +
|l1d extra=
 +
|l2 cache=64 KiB
 +
|l2 break=1x64 KiB
 +
|l2 desc=16-way set associative
 +
|l2 extra=
 +
|l3 cache=
 +
|l3 break=
 +
|l3 desc=
 +
|l3 extra=
 +
}}
 +
 
 +
== Graphics ==
 +
This SoC has no integrated graphics processing unit.
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 +
== Features ==
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{{x86 features
 +
| em64t      =
 +
| nx          =
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| txt        =
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| tsx        =
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| vpro        =
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| ht          =
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| tbt1        =
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| tbt2        =
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| bpt        =
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| vt-x        =
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| vt-d        =
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| ept        =
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| mmx        = Yes
 +
| emmx        = Yes
 +
| 3dnow      = Yes
 +
| e3dnow      = Yes
 +
| sse        =
 +
| sse2        =
 +
| sse3        =
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| ssse3      =
 +
| sse4        =
 +
| sse4.1      =
 +
| sse4.2      =
 +
| aes        =
 +
| pclmul      =
 +
| avx        =
 +
| avx2        =
 +
| bmi        =
 +
| bmi1        =
 +
| bmi2        =
 +
| f16c        =
 +
| fma3        =
 +
| mpx        =
 +
| sgx        =
 +
| eist        =
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}}
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* [[has feature::Halt State]]
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* [[has feature::Sleep State]]
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 +
== Documents ==
 +
=== DataSheet ===
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* [[:File:AMD Duron Processor Model 3 Data Sheet (June, 2001).pdf|AMD Duron Processor Model 3 Data Sheet]]; Publication # 23802; Rev: I; Issue Date: June 2001.
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=== Other ===
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* [[:File:AMD Duron Processor Model 3 Revision Guide (October, 2003).pdf|AMD Duron Processor Model 3 Revision Guide]]; Publication # 23865; Rev: K; Issue Date: October 2003.
 +
 
 +
== Gallery ==
 +
<gallery>
 +
File:AMD Duron D600AUT1B.jpg
 +
</gallery>

Latest revision as of 15:07, 13 December 2017

Edit Values
Duron 600
KL AMD Duron Spitfire.jpg
General Info
DesignerAMD
ManufacturerAMD
Model NumberDuron 600
Part NumberD600AUT1B,
D0600AUT1B
MarketDesktop
IntroductionJune 5, 2000 (announced)
June 19, 2000 (launched)
ShopAmazon
General Specs
FamilyDuron
SeriesDuron Desktop
LockedYes
Frequency600 MHz
Bus typeFSB
Bus speed100 MHz
Bus rate200 MT/s
Clock multiplier6
CPUID630
Microarchitecture
MicroarchitectureK7
Core NameSpitfire
Core Family6
Core Model3
Core Stepping0
Process180 nm
Transistors25,000,000
TechnologyCMOS
Die100 mm²
Word Size32 bit
Cores1
Threads1
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1.6 V ± 0.1 V
TDP27.4 W
Tcase0 °C – 90 °C
Tstorage-40 °C – 100 °C

Duron 600 based on the Spitfire core was a 32-bit x86 microprocessor developed by AMD and introduced in 2000. This model was part of the first series of the Duron family. Designed based on AMD's K7 (a Thunderbird-derivative) on a 180 nm process, this MPU operated at 550 MHz with a bus capable of 200 MT/s with a typical TDP of 27.4 W.

Cache[edit]

Main article: K7 § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L1D$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L2$ 64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
1x64 KiB 16-way set associative

Graphics[edit]

This SoC has no integrated graphics processing unit.

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
3DNow!3DNow! Extension
E3DNow!Extended 3DNow! Extension
  • Halt State
  • Sleep State

Documents[edit]

DataSheet[edit]

Other[edit]

Gallery[edit]

  • AMD Duron D600AUT1B.jpg
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Facts about "Duron 600 (Spitfire) - AMD"
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has featureHalt State + and Sleep State +
l1d$ description2-way set associative +
l1i$ description2-way set associative +
l2$ description16-way set associative +