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Difference between revisions of "amd/k6-2/k6-2-300bnz"
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{{amd title|AMD-K6-2/300BNZ}} | {{amd title|AMD-K6-2/300BNZ}} | ||
| − | {{ | + | {{chip |
| name = K6-2/300BNZ | | name = K6-2/300BNZ | ||
| no image = No | | no image = No | ||
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| manufacturer = AMD | | manufacturer = AMD | ||
| model number = K6-2/300BNZ | | model number = K6-2/300BNZ | ||
| − | | part number = K6-2/300BNZ | + | | part number = AMD-K6-2/300BNZ |
| − | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Mobile | | market = Mobile | ||
| first announced = March 22, 1999 | | first announced = March 22, 1999 | ||
| Line 44: | Line 44: | ||
| thread count = 1 | | thread count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| + | |||
| − | |||
| power = 10 W | | power = 10 W | ||
| v core = 1.8 V | | v core = 1.8 V | ||
| Line 78: | Line 78: | ||
== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k6-2#Memory_Hierarchy|l1=K6-2 § Cache}} | {{main|amd/microarchitectures/k6-2#Memory_Hierarchy|l1=K6-2 § Cache}} | ||
| − | [[L2$]] can be 512 | + | [[L2$]] can be 512 KiB to 1 MiB, depending on manufacturer and [[motherboard]] model. L2$ is off-chip. |
{{cache info | {{cache info | ||
| − | |l1i cache=32 | + | |l1i cache=32 KiB |
| − | |l1i break=1x32 | + | |l1i break=1x32 KiB |
|l1i desc=2-way set associative | |l1i desc=2-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=32 | + | |l1d cache=32 KiB |
| − | |l1d break=1x32 | + | |l1d break=1x32 KiB |
|l1d desc=2-way set associative | |l1d desc=2-way set associative | ||
|l1d extra= | |l1d extra= | ||
| Line 102: | Line 102: | ||
== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| mmx = true | | mmx = true | ||
| 3dnow = true | | 3dnow = true | ||
Latest revision as of 15:08, 13 December 2017
| Edit Values | |
| K6-2/300BNZ | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | K6-2/300BNZ |
| Part Number | AMD-K6-2/300BNZ |
| Market | Mobile |
| Introduction | March 22, 1999 (announced) March 22, 1999 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | K6-2 |
| Series | K6-2 Mobile |
| Frequency | 299.99 MHz |
| Bus type | FSB |
| Bus speed | 99.99 MHz |
| Bus rate | 99.99 MT/s |
| Clock multiplier | 3 |
| CPUID | 58C |
| Microarchitecture | |
| Microarchitecture | K6-2 |
| Platform | Super 7 |
| Core Name | Chomper Extended |
| Core Family | 5 |
| Core Model | 8 |
| Core Stepping | 12 |
| Process | 0.25 µm |
| Transistors | 9,300,000 |
| Technology | CMOS |
| Die | 81 mm² |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 10 W |
| Vcore | 1.8 V ± 0.1 V |
| VI/O | 3.3675 V ± 7% |
| Tcase | 0 °C – 85 °C |
| Tstorage | -65 °C – 150 °C |
K6-2/300BNZ was a 32-bit x86 K6-2-based mobile microprocessor designed and manufactured in 1999 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 300 MHz with a FSB operating at 100 MHz.
Contents
Cache[edit]
- Main article: K6-2 § Cache
L2$ can be 512 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
| L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
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- Auto-power down state
- Stop clock state
Documents[edit]
DataSheet[edit]
- Mobile AMD-K6-2 Processor Data Sheet; Publication #21896 Revision E/0, May 2000
Facts about "AMD-K6-2/300BNZ - AMD"
| l1d$ description | 2-way set associative + |
| l1i$ description | 2-way set associative + |