Semiconductor & Computer Engineering
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Difference between revisions of "amd/k6/amd-k6/300afr"
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{{amd title|AMD-K6/300AFR}} | {{amd title|AMD-K6/300AFR}} | ||
| − | {{ | + | {{chip |
| name = AMD-K6/300AFR | | name = AMD-K6/300AFR | ||
| no image = | | no image = | ||
| Line 43: | Line 43: | ||
| thread count = 1 | | thread count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| max memory addr = | | max memory addr = | ||
| − | + | ||
| power = 15.4 W | | power = 15.4 W | ||
| v core = 2.2 V | | v core = 2.2 V | ||
| Line 57: | Line 57: | ||
| tjunc max = | | tjunc max = | ||
| tcase min = 0 °C | | tcase min = 0 °C | ||
| − | | tcase max = | + | | tcase max = 70 °C |
| tstorage min = -65 °C | | tstorage min = -65 °C | ||
| tstorage max = 150 °C | | tstorage max = 150 °C | ||
| Line 76: | Line 76: | ||
== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k6#Memory_Hierarchy|l1=K6 § Cache}} | {{main|amd/microarchitectures/k6#Memory_Hierarchy|l1=K6 § Cache}} | ||
| − | [[L2$]] can be 256 | + | [[L2$]] can be 256 KiB to 1 MiB, depending on manufacturer and [[motherboard]] model. L2$ is off-chip. |
{{cache info | {{cache info | ||
| − | |l1i cache=32 | + | |l1i cache=32 KiB |
| − | |l1i break=1x32 | + | |l1i break=1x32 KiB |
|l1i desc=2-way set associative | |l1i desc=2-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=32 | + | |l1d cache=32 KiB |
| − | |l1d break=1x32 | + | |l1d break=1x32 KiB |
|l1d desc=2-way set associative | |l1d desc=2-way set associative | ||
|l1d extra= | |l1d extra= | ||
| Line 100: | Line 100: | ||
== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| mmx = true | | mmx = true | ||
}} | }} | ||
Latest revision as of 15:09, 13 December 2017
| Edit Values | |
| AMD-K6/300AFR | |
 | |
| 300AFR, Week 23, 1998 | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | AMD-K6/300AFR |
| Part Number | AMD-K6/300AFR |
| Market | Desktop |
| Introduction | January, 1998 (announced) March 5, 1998 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | K6 |
| Series | Desktop K6 |
| Locked | No |
| Frequency | 299.99 MHz |
| Bus type | FSB |
| Bus speed | 66.66 MHz |
| Bus rate | 66.66 MT/s |
| Clock multiplier | 4.5 |
| CPUID | 570 |
| Microarchitecture | |
| Microarchitecture | K6 |
| Core Name | Little Foot |
| Core Family | 5 |
| Core Model | 7 |
| Process | 250 nm |
| Transistors | 8,800,000 |
| Technology | CMOS |
| Die | 68 mm² |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 15.4 W |
| Vcore | 2.2 V ± 5% |
| VI/O | 3.3 V ± 5% |
| Tcase | 0 °C – 70 °C |
| Tstorage | -65 °C – 150 °C |
AMD-K6/300AFR was a 32-bit x86 microprocessor designed by AMD and introduced in early 1998. This chip, which was based on AMD's new K6 microarchitecture, operated at 300 MHz and dissipated a maximum of 15.4 W.
Cache[edit]
- Main article: K6 § Cache
L2$ can be 256 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
| L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
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- Auto-power down state
- Stop clock state
Gallery[edit]
300AFR, Week 34, 1998
300AFR, Week 14, 1998
Documents[edit]
DataSheet[edit]
- AMD-K6 Processor Data Sheet; Publication #20695 Revision H/0; March 1998
Facts about "AMD-K6/300AFR - AMD"
| l1d$ description | 2-way set associative + |
| l1i$ description | 2-way set associative + |