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{{amd title|AMD-K6-233AFR}}
 
{{amd title|AMD-K6-233AFR}}
{{mpu
+
{{chip
 
| name                = AMD-K6-233AFR
 
| name                = AMD-K6-233AFR
 
| no image            = Yes
 
| no image            = Yes
Line 43: Line 43:
 
| thread count        = 1
 
| thread count        = 1
 
| max cpus            = 1
 
| max cpus            = 1
| max memory          = 4 GB
+
| max memory          = 4 GiB
 
| max memory addr    =  
 
| max memory addr    =  
  
| microarch          = K6
 
| platform            =
 
| chipset            =
 
| core name          = 6k86
 
| core family        = 5
 
| core model          = 6
 
| core stepping      =
 
| core stepping 2    =
 
| process            = 350 nm
 
| transistors        = 8,800,000
 
| technology          = CMOS
 
| die size            = 162 mm²
 
| word size          = 32 bit
 
| core count          = 1
 
| thread count        = 1
 
| max cpus            = 1
 
| max memory          = 4 GB
 
| max memory addr    =
 
  
| electrical          = Yes
 
 
| power              = 28.3 W
 
| power              = 28.3 W
 
| v core              = 2.9 V
 
| v core              = 2.9 V
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}}
 
}}
 
'''AMD-K6-233AFR''' was a {{arch|32}} [[x86]] microprocessor designed by [[AMD]] and introduced in early [[1997]]. This chip, which was based on AMD's new {{amd|microarchitectures/k6|K6 microarchitecture}}, operated at 233 MHz and dissipated a maximum of 28.3 W.
 
'''AMD-K6-233AFR''' was a {{arch|32}} [[x86]] microprocessor designed by [[AMD]] and introduced in early [[1997]]. This chip, which was based on AMD's new {{amd|microarchitectures/k6|K6 microarchitecture}}, operated at 233 MHz and dissipated a maximum of 28.3 W.
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 +
== Cache ==
 +
{{main|amd/microarchitectures/k6#Memory_Hierarchy|l1=K6 § Cache}}
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[[L2$]] can be 256 KiB to 1 MiB, depending on manufacturer and [[motherboard]] model. L2$ is off-chip.
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{{cache info
 +
|l1i cache=32 KiB
 +
|l1i break=1x32 KiB
 +
|l1i desc=2-way set associative
 +
|l1i extra=
 +
|l1d cache=32 KiB
 +
|l1d break=1x32 KiB
 +
|l1d desc=2-way set associative
 +
|l1d extra=
 +
|l2 cache=
 +
|l2 break=
 +
|l2 desc=
 +
|l2 extra=
 +
|l3 cache=
 +
|l3 break=
 +
|l3 desc=
 +
|l3 extra=
 +
}}
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 +
== Graphics ==
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This SoC has no integrated graphics processing unit.
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 +
== Features ==
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{{x86 features
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| mmx = true
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}}
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* Auto-power down state
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* Stop clock state
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== Documents ==
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=== DataSheet ===
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* [[:File:AMD-K6 Processor DataSheet (March, 1998).pdf|AMD-K6 Processor Data Sheet]]; Publication #20695 Revision H/0; March 1998

Latest revision as of 15:09, 13 December 2017

Edit Values
AMD-K6-233AFR
General Info
DesignerAMD
ManufacturerAMD
Model NumberAMD-K6-233AFR
Part NumberAMD-K6-233AFR
MarketDesktop
IntroductionMay, 1997 (announced)
May, 1997 (launched)
ShopAmazon
General Specs
FamilyK6
SeriesDesktop K6
LockedNo
Frequency233.33 MHz
Bus typeFSB
Bus speed66.66 MHz
Bus rate66.66 MT/s
Clock multiplier3.5
CPUID560
Microarchitecture
MicroarchitectureK6
Core Name6k86
Core Family5
Core Model6
Process350 nm
Transistors8,800,000
TechnologyCMOS
Die162 mm²
Word Size32 bit
Cores1
Threads1
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation28.3 W
Vcore2.9 V ± 5%
VI/O3.3 V ± 5%
Tcase0 °C – 70 °C
Tstorage-65 °C – 150 °C

AMD-K6-233AFR was a 32-bit x86 microprocessor designed by AMD and introduced in early 1997. This chip, which was based on AMD's new K6 microarchitecture, operated at 233 MHz and dissipated a maximum of 28.3 W.

Cache[edit]

Main article: K6 § Cache

L2$ can be 256 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.

Cache Info [Edit Values]
L1I$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative
L1D$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative

Graphics[edit]

This SoC has no integrated graphics processing unit.

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
  • Auto-power down state
  • Stop clock state

Documents[edit]

DataSheet[edit]

Facts about "AMD-K6-233AFR - AMD"
l1d$ description2-way set associative +
l1i$ description2-way set associative +