Semiconductor & Computer Engineering
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Difference between revisions of "amd/k5/amd-k5-pr100abq"
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{{amd title|AMD-K5-PR100ABQ}} | {{amd title|AMD-K5-PR100ABQ}} | ||
| − | {{ | + | {{chip |
| name = AMD-K5-PR100ABQ | | name = AMD-K5-PR100ABQ | ||
| no image = | | no image = | ||
| Line 10: | Line 10: | ||
| model number = AMD-K5-PR100ABQ | | model number = AMD-K5-PR100ABQ | ||
| part number = AMD-K5-PR100ABQ | | part number = AMD-K5-PR100ABQ | ||
| − | | part number | + | | part number 2 = |
| market = Desktop | | market = Desktop | ||
| first announced = June 17, 1996 | | first announced = June 17, 1996 | ||
| Line 42: | Line 42: | ||
| thread count = 1 | | thread count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| max memory addr = 0xFFFFFFFF | | max memory addr = 0xFFFFFFFF | ||
| − | + | ||
| power = 15.8 W | | power = 15.8 W | ||
| v core = 3.525 V | | v core = 3.525 V | ||
| Line 77: | Line 77: | ||
== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k5#Memory_Hierarchy|l1=K5 § Cache}} | {{main|amd/microarchitectures/k5#Memory_Hierarchy|l1=K5 § Cache}} | ||
| − | |||
{{cache info | {{cache info | ||
| − | |l1i cache=16 | + | |l1i cache=16 KiB |
| − | |l1i break=1x16 | + | |l1i break=1x16 KiB |
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=8 | + | |l1d cache=8 KiB |
| − | |l1d break=1x8 | + | |l1d break=1x8 KiB |
|l1d desc=4-way set associative | |l1d desc=4-way set associative | ||
|l1d extra= | |l1d extra= | ||
| Line 101: | Line 100: | ||
== Features == | == Features == | ||
| + | * [[processor p-rating::P100]] [[P-Rating]] | ||
* Auto-power down state | * Auto-power down state | ||
* Stop clock state | * Stop clock state | ||
Latest revision as of 15:07, 13 December 2017
| Edit Values | |
| AMD-K5-PR100ABQ | |
 | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | AMD-K5-PR100ABQ |
| Part Number | AMD-K5-PR100ABQ |
| Market | Desktop |
| Introduction | June 17, 1996 (announced) June 17, 1996 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | K5 |
| Series | SSA/5 |
| Frequency | 99.99 MHz |
| Bus type | FSB |
| Bus speed | 66.66 MHz |
| Bus rate | 66.66 MT/s |
| Clock multiplier | 1.5 |
| CPUID | 501 |
| Microarchitecture | |
| Microarchitecture | K5 |
| Core Name | SSA/5 |
| Core Family | 5 |
| Core Model | 0 |
| Core Stepping | 1 |
| Process | 350 nm |
| Transistors | 4,300,000 |
| Technology | CMOS |
| Die | 161 mm² |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 4 GiB |
| Max Address Mem | 0xFFFFFFFF |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 15.8 W |
| Vcore | 3.525 V ± 2% |
| Tcase | 0 °C – 60 °C |
| Tstorage | -65°C – 150 °C |
AMD-K5-PR100ABQ was a 32-bit x86 microprocessor developed by AMD and released in 1996. This chip was sold as Pentium 100 MHz equivalent. The processor used AMD's 2nd revision of their K5 microarchitecture, operating at 100 MHz with a TDP of 15.8 W.
Contents
Cache[edit]
- Main article: K5 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative |
| L1D$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
- P100 P-Rating
- Auto-power down state
- Stop clock state
Gallery[edit]
.jpg)
See also[edit]
Facts about "AMD-K5-PR100ABQ - AMD"
| l1d$ description | 4-way set associative + |
| l1i$ description | 4-way set associative + |