Semiconductor & Computer Engineering
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Difference between revisions of "amd/k5/amd-ssa-5-75abr"
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{{amd title|AMD-SSA/5-75ABR}} | {{amd title|AMD-SSA/5-75ABR}} | ||
| − | {{ | + | {{chip |
| name = AMD-SSA/5-75ABR | | name = AMD-SSA/5-75ABR | ||
| no image = | | no image = | ||
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| model number = AMD-SSA/5-75ABR | | model number = AMD-SSA/5-75ABR | ||
| part number = AMD-SSA/5-75ABR | | part number = AMD-SSA/5-75ABR | ||
| − | | part number | + | | part number 2 = |
| market = Desktop | | market = Desktop | ||
| first announced = 1996 | | first announced = 1996 | ||
| Line 42: | Line 42: | ||
| thread count = 1 | | thread count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| max memory addr = 0xFFFFFFFF | | max memory addr = 0xFFFFFFFF | ||
| − | + | ||
| power = | | power = | ||
| v core = 3.525 V | | v core = 3.525 V | ||
| Line 77: | Line 77: | ||
== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k5#Memory_Hierarchy|l1=K5 § Cache}} | {{main|amd/microarchitectures/k5#Memory_Hierarchy|l1=K5 § Cache}} | ||
| − | |||
{{cache info | {{cache info | ||
| − | |l1i cache=16 | + | |l1i cache=16 KiB |
| − | |l1i break=1x16 | + | |l1i break=1x16 KiB |
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=8 | + | |l1d cache=8 KiB |
| − | |l1d break=1x8 | + | |l1d break=1x8 KiB |
|l1d desc=4-way set associative | |l1d desc=4-way set associative | ||
|l1d extra= | |l1d extra= | ||
| Line 101: | Line 100: | ||
== Features == | == Features == | ||
| + | * [[processor p-rating::P75]] [[P-Rating]] | ||
* Auto-power down state | * Auto-power down state | ||
* Stop clock state | * Stop clock state | ||
| + | |||
| + | == Gallery == | ||
| + | <gallery> | ||
| + | File:Die amd 5k86-P75 SSA5-75BR.jpg|Chip de-capped | ||
| + | File:Ic-photo-AMD--AMD-SSA 5-75ABR-(AMD5k86-P75-CPU).png | ||
| + | </gallery> | ||
== See also == | == See also == | ||
* {{amd|K5}} | * {{amd|K5}} | ||
Latest revision as of 15:08, 13 December 2017
| Edit Values | |
| AMD-SSA/5-75ABR | |
 | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | AMD-SSA/5-75ABR |
| Part Number | AMD-SSA/5-75ABR |
| Market | Desktop |
| Introduction | 1996 (announced) March 27, 1996 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | K5 |
| Series | SSA/5 |
| Frequency | 75 MHz |
| Bus type | FSB |
| Bus speed | 50 MHz |
| Bus rate | 50 MT/s |
| Clock multiplier | 1.5 |
| CPUID | 500 |
| Microarchitecture | |
| Microarchitecture | K5 |
| Core Name | SSA/5 |
| Core Family | 5 |
| Core Model | 0 |
| Core Stepping | 0 |
| Process | 500 nm |
| Transistors | 4,300,000 |
| Technology | CMOS |
| Die | 251 mm² |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 4 GiB |
| Max Address Mem | 0xFFFFFFFF |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Vcore | 3.525 V ± 2% |
| Tcase | 0 °C – 70 °C |
| Tstorage | -65°C – 150 °C |
AMD-SSA/5-75ABR was a 32-bit x86 microprocessor developed by AMD and released in 1996. This processor was the first of AMD's brand new K5 microarchitecture designed entirely in-house. The chip operated at 75 MHz.
Contents
Cache[edit]
- Main article: K5 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative |
| L1D$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
- P75 P-Rating
- Auto-power down state
- Stop clock state
Gallery[edit]
Chip de-capped
.png)
See also[edit]
Facts about "AMD-SSA/5-75ABR - AMD"
| l1d$ description | 4-way set associative + |
| l1i$ description | 4-way set associative + |