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Difference between revisions of "amd/am186/in80c186"
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{{amd title|IN80C186}} | {{amd title|IN80C186}} | ||
− | {{ | + | {{chip |
| name = IN80C186 | | name = IN80C186 | ||
| no image = Yes | | no image = Yes | ||
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| model number = IN80C186 | | model number = IN80C186 | ||
| part number = IN80C186 | | part number = IN80C186 | ||
− | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Embedded | | market = Embedded | ||
| first announced = | | first announced = | ||
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| core count = 1 | | core count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
− | | max memory = 1 | + | | max memory = 1 MiB |
| max memory addr = | | max memory addr = | ||
− | + | ||
| power = 1 W | | power = 1 W | ||
| v core = 5 V | | v core = 5 V | ||
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{{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}} | {{main|intel/microarchitectures/80186#Memory_Hierarchy|l1=80186 § Cache}} | ||
{{cache info | {{cache info | ||
− | |l1 cache=0 | + | |l1 cache=0 KiB |
− | |l1 break=1x0 | + | |l1 break=1x0 KiB |
|l1 desc= | |l1 desc= | ||
|l1 extra= | |l1 extra= | ||
− | |l2 cache=0 | + | |l2 cache=0 KiB |
− | |l2 break=1x0 | + | |l2 break=1x0 KiB |
}} | }} | ||
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* Power saving mode | * Power saving mode | ||
* DRAM Refresh Control Unit | * DRAM Refresh Control Unit | ||
+ | |||
+ | == Documents == | ||
+ | * [[:File:AMD 80C186 (June 1994).pdf|AMD 80C186 (June 1994)]], Publication #17907 Rev B |
Latest revision as of 14:17, 13 December 2017
Edit Values | |
IN80C186 | |
General Info | |
Manufacturer | AMD |
Model Number | IN80C186 |
Part Number | IN80C186 |
Market | Embedded |
General Specs | |
Family | Am186 |
Series | Am186 |
Frequency | 10 MHz |
Bus speed | 2.5 MHz |
Bus rate | 2.5 MT/s |
Microarchitecture | |
Microarchitecture | 80186 |
Core Name | 80186 |
Technology | CMOS |
Word Size | 16 bit |
Cores | 1 |
Max Memory | 1 MiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Power dissipation | 1 W |
Vcore | 5 V ± 5 % |
Tcase | -40 °C – 85 °C |
Tstorage | -65 °C – 150 °C |
IN80C186 is an 80186-based microprocessor manufactured by AMD. This model is a redesigned CMOS version that operated at 10 MHz and introduced a number of enhancements in addition to being lower-power CMOS, including a DRAM Refresh Control Unit and various power saving modes. This model is an industrial version of the N80C186.
Contents
Cache[edit]
- Main article: 80186 § Cache
Cache Info [Edit Values] | ||
L1$ | 0 KiB 0 B 0 MiB |
1x0 KiB |
L2$ | 0 KiB 0 MiB 0 B 0 GiB |
1x0 KiB |
Graphics[edit]
This chip had no integrated graphics processing unit.
Features[edit]
- Industrial temperature range
- 10 new instructions
- Two DMA channels
- Three programmable interrupt timers
- Local Bus Controller
- Object code-compatible with all 86/88 software
- Power saving mode
- DRAM Refresh Control Unit
Documents[edit]
- AMD 80C186 (June 1994), Publication #17907 Rev B
Facts about "IN80C186 - AMD"
base frequency | 10 MHz (0.01 GHz, 10,000 kHz) + |
bus rate | 2.5 MT/s (0.0025 GT/s, 2,500 kT/s) + |
bus speed | 2.5 MHz (0.0025 GHz, 2,500 kHz) + |
core count | 1 + |
core name | 80186 + |
core voltage | 5 V (50 dV, 500 cV, 5,000 mV) + |
core voltage tolerance | 5 % + |
family | Am186 + |
full page name | amd/am186/in80c186 + |
instance of | microprocessor + |
l1$ size | 0 KiB (0 B, 0 MiB) + |
l2$ size | 0 MiB (0 KiB, 0 B, 0 GiB) + |
ldate | 1900 + |
manufacturer | AMD + |
market segment | Embedded + |
max case temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
max cpu count | 1 + |
max memory | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB, 9.536743e-7 TiB) + |
max storage temperature | 423.15 K (150 °C, 302 °F, 761.67 °R) + |
microarchitecture | 80186 + |
min case temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
min storage temperature | 208.15 K (-65 °C, -85 °F, 374.67 °R) + |
model number | IN80C186 + |
name | IN80C186 + |
part number | IN80C186 + |
power dissipation | 1 W (1,000 mW, 0.00134 hp, 0.001 kW) + |
series | Am186 + |
smp max ways | 1 + |
technology | CMOS + |
word size | 16 bit (2 octets, 4 nibbles) + |