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Difference between revisions of "intel/xeon e3/e3-1284l v3"
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{{intel title|Xeon E3-1284L v3}} | {{intel title|Xeon E3-1284L v3}} | ||
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| name = Intel Xeon E3-1284L v3 | | name = Intel Xeon E3-1284L v3 | ||
| image = | | image = | ||
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| locked = Yes | | locked = Yes | ||
| frequency = 1800 MHz | | frequency = 1800 MHz | ||
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| turbo frequency1 = 3200 MHz | | turbo frequency1 = 3200 MHz | ||
| turbo frequency2 = 3100 MHz | | turbo frequency2 = 3100 MHz | ||
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| thread count = 8 | | thread count = 8 | ||
| max cpus = 1 | | max cpus = 1 | ||
− | | max memory = 32 | + | | max memory = 32 GiB |
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| tdp = 47 W | | tdp = 47 W | ||
| temp max = 100 C | | temp max = 100 C | ||
− | + | |package module 1={{packages/intel/fcbga-1364}} | |
− | | package | ||
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}} | }} | ||
The '''Intel Xeon E3-1284L v3''' is a [[quad core]] [[64-bit architecture|64-bit]] server [[microprocessor]] released by [[Intel]] in 2014. The microprocessor is based on the [[Haswell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. | The '''Intel Xeon E3-1284L v3''' is a [[quad core]] [[64-bit architecture|64-bit]] server [[microprocessor]] released by [[Intel]] in 2014. The microprocessor is based on the [[Haswell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. | ||
== Cache == | == Cache == | ||
+ | {{main|intel/microarchitectures/haswell#Memory_Hierarchy|l1=Haswell § Cache}} | ||
This specific microprocessor includes the [[has feature::Crystal Well]] cache. | This specific microprocessor includes the [[has feature::Crystal Well]] cache. | ||
{{cache info | {{cache info | ||
− | |l1i cache=128 | + | |l1i cache=128 KiB |
− | |l1i break=4x32 | + | |l1i break=4x32 KiB |
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
|l1i extra=(per core, write-back) | |l1i extra=(per core, write-back) | ||
− | |l1d cache=128 | + | |l1d cache=128 KiB |
− | |l1d break=4x32 | + | |l1d break=4x32 KiB |
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
|l1d extra=(per core, write-back) | |l1d extra=(per core, write-back) | ||
− | |l2 cache=1 | + | |l2 cache=1 MiB |
− | |l2 break=4x256 | + | |l2 break=4x256 KiB |
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
|l2 extra=(per core, write-back) | |l2 extra=(per core, write-back) | ||
− | |l3 cache=6 | + | |l3 cache=6 MiB |
− | |l3 desc=shared | + | |l3 desc=12-way set associative |
− | |l4 cache=128 | + | |l3 extra=(shared) |
+ | |l4 cache=128 MiB | ||
|l4 desc=16-way set associative | |l4 desc=16-way set associative | ||
|l4 extra=(see {{intel|Crystal Well}}) | |l4 extra=(see {{intel|Crystal Well}}) | ||
Line 84: | Line 80: | ||
| frequency = 200 MHz | | frequency = 200 MHz | ||
| max frequency = 750 MHz | | max frequency = 750 MHz | ||
− | | max memory = | + | | max memory = 1 GiB |
| output edp = Yes | | output edp = Yes | ||
| output dp = Yes | | output dp = Yes | ||
Line 111: | Line 107: | ||
== Features == | == Features == | ||
− | {{ | + | {{x86 features |
| em64t = Yes | | em64t = Yes | ||
| nx = Yes | | nx = Yes |
Latest revision as of 16:27, 13 December 2017
Edit Values | |||||||||||||
Intel Xeon E3-1284L v3 | |||||||||||||
General Info | |||||||||||||
Designer | Intel | ||||||||||||
Manufacturer | Intel | ||||||||||||
Model Number | E3-1284L v3 | ||||||||||||
Part Number | CL8064701637600 | ||||||||||||
S-Spec | SR1U0 | ||||||||||||
Market | Server | ||||||||||||
Introduction | Mar 1, 2014 (announced) October 1, 2014 (launched) | ||||||||||||
Shop | Amazon | ||||||||||||
General Specs | |||||||||||||
Family | Xeon E3 | ||||||||||||
Locked | Yes | ||||||||||||
Frequency | 1800 MHz | ||||||||||||
Turbo Frequency | 3200 MHz (1 core), 3100 MHz (2 cores), 3000 MHz (3 cores), 3000 MHz (4 cores) | ||||||||||||
Bus type | DMI 2.0 | ||||||||||||
Bus rate | 5 GT/s | ||||||||||||
Clock multiplier | 18 | ||||||||||||
Microarchitecture | |||||||||||||
Microarchitecture | Haswell | ||||||||||||
Core Stepping | C0 | ||||||||||||
Process | 22 nm | ||||||||||||
Word Size | 64 bits | ||||||||||||
Cores | 4 | ||||||||||||
Threads | 8 | ||||||||||||
Max Memory | 32 GiB | ||||||||||||
Multiprocessing | |||||||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||||||
Electrical | |||||||||||||
TDP | 47 W | ||||||||||||
OP Temperature | – 100 C | ||||||||||||
Packaging | |||||||||||||
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The Intel Xeon E3-1284L v3 is a quad core 64-bit server microprocessor released by Intel in 2014. The microprocessor is based on the Haswell microarchitecture. This MPU includes the Intel Iris Pro 5200 integrated graphic and features the 128 MB L4$ Crystal Well cache.
Contents
Cache[edit]
- Main article: Haswell § Cache
This specific microprocessor includes the Crystal Well cache.
Cache Info [Edit Values] | ||
L1I$ | 128 KiB 131,072 B 0.125 MiB |
4x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 128 KiB 131,072 B 0.125 MiB |
4x32 KiB 8-way set associative (per core, write-back) |
L2$ | 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB |
4x256 KiB 8-way set associative (per core, write-back) |
L3$ | 6 MiB 6,144 KiB 6,291,456 B 0.00586 GiB |
12-way set associative (shared) |
L4$ | 128 MiB 131,072 KiB 134,217,728 B 0.125 GiB |
16-way set associative (see Crystal Well) |
Graphics[edit]
Integrated Graphic Information | |
GPU | Intel Iris Pro Graphics 5200 |
Displays | 3 |
Frequency | 200 MHz 0.2 GHz
200,000 KHz |
Max frequency | 750 MHz 0.75 GHz
750,000 KHz |
Max memory | 1 GiB 1,024 MiB
1,048,576 KiB 1,073,741,824 B |
Output | DisplayPort, Embedded DisplayPort, HDMI, VGA |
Memory controller[edit]
Integrated Memory Controller | |
Type | DDR3L-1333, DDR3L-1600 |
Controllers | 1 |
Channels | 2 |
ECC Support | Yes |
Max bandwidth | 25,600 MB/s |
Max memory | 32,768 MB |
Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Xeon E3-1284L v3 - Intel"
has feature | Crystal Well + and integrated gpu + |
integrated gpu | Intel Iris Pro Graphics 5200 + |
integrated gpu base frequency | 200 MHz (0.2 GHz, 200,000 KHz) + |
integrated gpu max frequency | 750 MHz (0.75 GHz, 750,000 KHz) + |
l1d$ description | 8-way set associative + |
l1i$ description | 8-way set associative + |
l2$ description | 8-way set associative + |
l3$ description | shared + |
l4$ description | 16-way set associative + |
l4$ size | 128 MiB (131,072 KiB, 134,217,728 B, 0.125 GiB) + |