From WikiChip
Difference between revisions of "intel/core i7/i7-4770hq"
< intel‎ | core i7

m (Bot: moving all {{mpu}} to {{chip}})
 
(8 intermediate revisions by 2 users not shown)
Line 1: Line 1:
 
{{intel title|Core i7-4770HQ}}
 
{{intel title|Core i7-4770HQ}}
−
{{mpu
+
{{chip
 
| name              = Intel Core i7-4770HQ
 
| name              = Intel Core i7-4770HQ
 
| image              =  
 
| image              =  
Line 19: Line 19:
 
| locked            = Yes
 
| locked            = Yes
 
| frequency          = 2200 MHz
 
| frequency          = 2200 MHz
−
| turbo frequency    = yes
+
 
 
| turbo frequency1  = 3400 MHz
 
| turbo frequency1  = 3400 MHz
 
| turbo frequency2  = 3300 MHz
 
| turbo frequency2  = 3300 MHz
Line 40: Line 40:
 
| thread count      = 8
 
| thread count      = 8
 
| max cpus          = 1
 
| max cpus          = 1
−
| max memory        = 32 GB
+
| max memory        = 32 GiB
 +
 
  
−
| electrical        = Yes
 
 
| tdp                = 47 W
 
| tdp                = 47 W
 
| temp max          = 100 C
 
| temp max          = 100 C
  
−
| packaging          = Yes
+
|package module 1={{packages/intel/fcbga-1364}}
−
| package           = FCBGA1364
 
−
| package type      = FCBGA
 
−
| package pitch      =
 
−
| package size      = 37.5mm x 32mm x 1.65mm
 
−
| socket            = BGA1364
 
−
| socket type        = BGA
 
 
}}
 
}}
 
The '''Intel Core i7-4770HQ''' is a [[quad core]] [[64-bit architecture|64-bit]] [[microprocessor]] released by [[Intel]] in 2014. The microprocessor is based on the [[Haswell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
 
The '''Intel Core i7-4770HQ''' is a [[quad core]] [[64-bit architecture|64-bit]] [[microprocessor]] released by [[Intel]] in 2014. The microprocessor is based on the [[Haswell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  
 
== Cache ==
 
== Cache ==
 +
{{main|intel/microarchitectures/haswell#Memory_Hierarchy|l1=Haswell § Cache}}
 
This specific microprocessor includes the [[has feature::Crystal Well]] cache.
 
This specific microprocessor includes the [[has feature::Crystal Well]] cache.
 
{{cache info
 
{{cache info
−
|l1i cache=128 KB
+
|l1i cache=128 KiB
−
|l1i break=4x32 KB
+
|l1i break=4x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
 
|l1i extra=(per core, write-back)
 
|l1i extra=(per core, write-back)
−
|l1d cache=128 KB
+
|l1d cache=128 KiB
−
|l1d break=4x32 KB
+
|l1d break=4x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l1d extra=(per core, write-back)
 
|l1d extra=(per core, write-back)
−
|l2 cache=1 MB
+
|l2 cache=1 MiB
−
|l2 break=4x256 KB
+
|l2 break=4x256 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
|l2 extra=(per core, write-back)
 
|l2 extra=(per core, write-back)
−
|l3 cache=6 MB
+
|l3 cache=6 MiB
 
|l3 desc=12-way set associative
 
|l3 desc=12-way set associative
 
|l3 extra=(shared)
 
|l3 extra=(shared)
−
|l4 cache=128 MB
+
|l4 cache=128 MiB
 
|l4 desc=16-way set associative
 
|l4 desc=16-way set associative
 
|l4 extra=(see {{intel|Crystal Well}})
 
|l4 extra=(see {{intel|Crystal Well}})
Line 112: Line 107:
  
 
== Features ==
 
== Features ==
−
{{mpu features
+
{{x86 features
 
| em64t    = Yes
 
| em64t    = Yes
 
| nx        = Yes
 
| nx        = Yes

Latest revision as of 15:22, 13 December 2017

Edit Values
Intel Core i7-4770HQ
General Info
DesignerIntel
ManufacturerIntel
Model Numberi7-4770HQ
Part NumberCL8064701956100
S-SpecSR1ZW
MarketMobile
IntroductionJuly 20, 2014 (announced)
July 20, 2014 (launched)
ShopAmazon
General Specs
FamilyCore i7
LockedYes
Frequency2200 MHz
Turbo Frequency3400 MHz (1 core),
3300 MHz (2 cores),
3200 MHz (3 cores),
3200 MHz (4 cores)
Bus typeDMI 2.0
Bus rate5 GT/s
Clock multiplier22
Microarchitecture
MicroarchitectureHaswell
PlatformShark Bay
Core SteppingC0
Process22 nm
Word Size64 bits
Cores4
Threads8
Max Memory32 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP47 W
OP Temperature – 100 C
Packaging
PackageFCBGA-1364 (BGA)
Dimension37.4 mm x 32 mm
Pitch0.7 mm
Ball Count1364
Ball CompSAC405
InterconnectBGA-1364

The Intel Core i7-4770HQ is a quad core 64-bit microprocessor released by Intel in 2014. The microprocessor is based on the Haswell microarchitecture. This MPU includes the Intel Iris Pro 5200 integrated graphic and features the 128 MB L4$ Crystal Well cache.

Cache[edit]

Main article: Haswell § Cache

This specific microprocessor includes the Crystal Well cache.

Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L1D$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
4x256 KiB 8-way set associative (per core, write-back)
L3$ 6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
12-way set associative (shared)
L4$ 128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
16-way set associative (see Crystal Well)

Graphics[edit]

Integrated Graphic Information
GPU Intel Iris Pro Graphics 5200
Displays 3
Frequency 200 MHz
0.2 GHz
200,000 KHz
Max frequency 1200 MHz
1.2 GHz
1,200,000 KHz
Output DisplayPort, Embedded DisplayPort, HDMI, VGA
DirectX 11.2, 12
OpenGL 4.3
Max HDMI Res 3840x2160 @60 Hz
Max DP Res 3840x2160 @60 Hz
Max VGA Res 2880x1800 @60 Hz

Memory controller[edit]

Integrated Memory Controller
Type DDR3L-1333, DDR3L-1600
Controllers 1
Channels 2
ECC Support No
Max bandwidth 25,600 MB/s
Max memory 32,768 MB

Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i7/i7-4770hq&oldid=70730"
Facts about "Core i7-4770HQ - Intel"
RDF feed
has featureCrystal Well + and integrated gpu +
integrated gpuIntel Iris Pro Graphics 5200 +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu max frequency1,200 MHz (1.2 GHz, 1,200,000 KHz) +
l1d$ description8-way set associative +
l1i$ description8-way set associative +
l2$ description8-way set associative +
l3$ description12-way set associative +
l4$ description16-way set associative +