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Difference between revisions of "amd/am486/am486dx4-100nv8t"
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{{amd title|Am486DX4-100NV8T}} | {{amd title|Am486DX4-100NV8T}} | ||
| − | {{ | + | {{chip |
| name = Am486DX4-100NV8T | | name = Am486DX4-100NV8T | ||
| − | | no image = | + | | no image = |
| − | | image = | + | | image = Ic-photo-AMD--A80486DX4-100NV8T-(486-CPU).png |
| image size = | | image size = | ||
| − | | caption = | + | | caption = A80486DX4-100NV8T |
| designer = AMD | | designer = AMD | ||
| manufacturer = AMD | | manufacturer = AMD | ||
| model number = Am486DX4-100NV8T | | model number = Am486DX4-100NV8T | ||
| part number = A80486DX4-100NV8T | | part number = A80486DX4-100NV8T | ||
| − | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Desktop | | market = Desktop | ||
| first announced = | | first announced = | ||
| Line 25: | Line 25: | ||
| bus type = FSB | | bus type = FSB | ||
| bus speed = 33 MHz | | bus speed = 33 MHz | ||
| − | | bus rate = | + | | bus rate = 33 MT/s |
| clock multiplier = 3 | | clock multiplier = 3 | ||
| cpuid = | | cpuid = | ||
| Line 46: | Line 46: | ||
| thread count = | | thread count = | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| max memory addr = | | max memory addr = | ||
| − | + | ||
| power = 2.6 W | | power = 2.6 W | ||
| v core = 3.3 V | | v core = 3.3 V | ||
| Line 63: | Line 63: | ||
| packaging = Yes | | packaging = Yes | ||
| − | | package | + | | package 0 = CPGA-168 |
| − | | package type | + | | package 0 type = CPGA |
| − | | package pitch | + | | package 0 pins = 168 |
| − | | package | + | | package 0 pitch = 2.286 mm |
| − | | socket | + | | package 0 width = 44.069 mm |
| − | | socket 2 | + | | package 0 length = 44.069 mm |
| − | | socket 3 | + | | package 0 height = 3.556 mm |
| + | | socket 0 = Socket 1 | ||
| + | | socket 0 type = | ||
| + | | socket 0 2 = Socket 2 | ||
| + | | socket 0 2 type = | ||
| + | | socket 0 3 = Socket 3 | ||
| + | | socket 0 3 type = | ||
}} | }} | ||
| − | '''Am486DX2-100NV8T''' was an {{intel|80486}}-compatible microprocessor introduced by [[AMD]] in 1995 following the conclusion of the legal battle with Intel. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model is | + | '''Am486DX2-100NV8T''' was an {{intel|80486}}-compatible microprocessor introduced by [[AMD]] in 1995 following the conclusion of the legal battle with Intel. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model is is a modified version of {{\\|Am486DX4-100V8T}} (and earlier {{\\|Am486DX4-100}}) that {{amd|Am486#Larger Cache & Post-lawsuit|no longer included Intel's ICE microcode}}. |
== Cache == | == Cache == | ||
{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1 cache=8 | + | |l1 cache=8 KiB |
| − | |l1 break=1x8 | + | |l1 break=1x8 KiB |
|l1 desc=4-way set associative | |l1 desc=4-way set associative | ||
|l1 extra=(unified, write-through policy) | |l1 extra=(unified, write-through policy) | ||
| Line 84: | Line 90: | ||
== Graphics == | == Graphics == | ||
This chip had no integrated graphics processing unit. | This chip had no integrated graphics processing unit. | ||
| + | |||
| + | == Documents == | ||
| + | * [[:File:AMD Am486DX4 NV8T (July, 1995).pdf|AMD Am486DX4-100NV8T (July, 1995)]] | ||
| + | |||
| + | == Gallery == | ||
| + | <gallery> | ||
| + | File:Amd-am486dx4-100-wt.jpg| | ||
| + | File:AMD Am486 DX4 100 NV8T CPU.jpg| | ||
| + | File:Ic-photo-AMD--AM486DX4-100-(486-CPU).png| | ||
| + | </gallery> | ||
| + | |||
| + | == Die Shot == | ||
| + | [[File:AMD 80486DX4-100 die.JPG|400px]] | ||
== See also == | == See also == | ||
* {{amd|Am486|Am486 family}} | * {{amd|Am486|Am486 family}} | ||
Latest revision as of 14:19, 13 December 2017
| Edit Values | |
| Am486DX4-100NV8T | |
 | |
| A80486DX4-100NV8T | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | Am486DX4-100NV8T |
| Part Number | A80486DX4-100NV8T |
| Market | Desktop |
| Introduction | 1995 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | Am486 |
| Series | Am486DX4V |
| Frequency | 100 MHz |
| Bus type | FSB |
| Bus speed | 33 MHz |
| Bus rate | 33 MT/s |
| Clock multiplier | 3 |
| Microarchitecture | |
| Microarchitecture | 80486 |
| Core Name | 486DX4V |
| Process | 500 nm |
| Technology | CMOS |
| Word Size | 32 bit |
| Cores | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 2.6 W |
| Vcore | 3.3 V ± 0.3 V |
| OP Temperature | 0 °C – 85 °C |
Am486DX2-100NV8T was an 80486-compatible microprocessor introduced by AMD in 1995 following the conclusion of the legal battle with Intel. This processor had a clock multiplier of 3 having base frequency of 100 MHz with a bus frequency of 33 MHz. This model is is a modified version of Am486DX4-100V8T (and earlier Am486DX4-100) that no longer included Intel's ICE microcode.
Cache[edit]
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative (unified, write-through policy) |
Graphics[edit]
This chip had no integrated graphics processing unit.
Documents[edit]
Gallery[edit]
.png)
Die Shot[edit]
