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Difference between revisions of "intel/80486/486sx2-50"
< intel‎ | 80486

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{{intel title|i486SX2-50}}
 
{{intel title|i486SX2-50}}
{{mpu
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{{chip
 
| name                = Intel i486SX2-50
 
| name                = Intel i486SX2-50
| no image            = Yes
+
| image              = KL intel i486SX2.jpg
| image              =  
 
 
| image size          =  
 
| image size          =  
| caption            =  
+
| caption            = A80486SX2-50, S-Spec SX845
 
| designer            = Intel
 
| designer            = Intel
 
| manufacturer        = Intel
 
| manufacturer        = Intel
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| bus rate            = 25 MT/s
 
| bus rate            = 25 MT/s
 
| clock multiplier    = 2
 
| clock multiplier    = 2
| s-spec              =  
+
| s-spec              = SX845
 
| s-spec es          =  
 
| s-spec es          =  
| s-spec qs          =  
+
| s-spec qs          = Q0498
| cpuid              =  
+
| s-spec qs 2        = Q0576
 +
| cpuid              = 45B
  
 
| microarch          = 80486
 
| microarch          = 80486
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| core count          = 1
 
| core count          = 1
 
| max cpus            = 1
 
| max cpus            = 1
| max memory          = 4 GB
+
| max memory          = 4 GiB
  
| electrical          = Yes
+
 
| power              =  
+
| power              = 3.08 W
 
| v core              = 5 V
 
| v core              = 5 V
| v core tolerance    =  
+
| v core tolerance    = 5%
 
| temp max            = 85 °C
 
| temp max            = 85 °C
 
| temp min            = 0 °C
 
| temp min            = 0 °C
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| socket 3            = Socket 3
 
| socket 3            = Socket 3
 
}}
 
}}
 +
'''i486SX2-50''' was a fourth-generation [[x86]] [[microprocessor]] introduced by [[Intel]] in the early 1990s. This chip, which is based on the {{intel|microarchitectures/80486|80486 microarchitecture}}, had a clock doubler operating at 50 MHz, twice the bus speed. In contrast to the i486DX chips, the i486SX line had no functional [[FPU]] on-die.
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== Cache ==
 +
{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}}
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{{cache info
 +
|l1 cache=8 KiB
 +
|l1 break=1x8 KiB
 +
|l1 desc=4-way set associative
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|l1 extra=(unified, write-through policy)
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}}
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 +
== Graphics ==
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This chip had no integrated graphics processing unit.
 +
 +
== Features ==
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* {{intel|System Management Mode}} (SMM)
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 +
== Gallery ==
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<gallery>
 +
File:Ic-photo-intel-A80486SX2-50-(486SX2).png|A80486SX2-50, S-Spec SX845
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</gallery>
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 +
== See also ==
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* {{intel|80486|80486 family}}

Latest revision as of 15:14, 13 December 2017

Edit Values
Intel i486SX2-50
KL intel i486SX2.jpg
A80486SX2-50, S-Spec SX845
General Info
DesignerIntel
ManufacturerIntel
Model Numberi486SX2-50
Part NumberA80486SX2-50,
A80486SX250
S-SpecSX845
Q0498 (QS), Q0576 (QS)
ShopAmazon
General Specs
Family80486
Series486SX2
Frequency50 MHz
Bus typeFSB
Bus speed25 MHz
Bus rate25 MT/s
Clock multiplier2
CPUID45B
Microarchitecture
Microarchitecture80486
Core Name486SX2
Process800 nm
Transistors900,000
TechnologyCMOS
Word Size32 bit
Cores1
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation3.08 W
Vcore5 V ± 5%
OP Temperature0 °C – 85 °C

i486SX2-50 was a fourth-generation x86 microprocessor introduced by Intel in the early 1990s. This chip, which is based on the 80486 microarchitecture, had a clock doubler operating at 50 MHz, twice the bus speed. In contrast to the i486DX chips, the i486SX line had no functional FPU on-die.

Cache[edit]

Main article: 80486 § Cache
Cache Info [Edit Values]
L1$ 8 KiB
8,192 B
0.00781 MiB
1x8 KiB 4-way set associative (unified, write-through policy)

Graphics[edit]

This chip had no integrated graphics processing unit.

Features[edit]

Gallery[edit]

See also[edit]

Facts about "i486SX2-50 - Intel"
l1$ description4-way set associative +