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Difference between revisions of "intel/xeon e3/e3-1260l v5"
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− | {{intel title|Xeon E3-1260L | + | {{intel title|Xeon E3-1260L v5}} |
− | {{ | + | {{chip |
− | | name | + | |name=Xeon E3-1260L v5 |
− | + | |image=skylake dt (front).png | |
− | | image | + | |designer=Intel |
− | + | |manufacturer=Intel | |
− | + | |model number=E3-1260L v5 | |
− | | designer | + | |part number=CM8066201921903 |
− | | manufacturer | + | |s-spec=SR2CR |
− | | model number | + | |s-spec 2=SR2LH |
− | | part number | + | |market=Server |
− | | market | + | |first announced=October 19, 2015 |
− | | first announced | + | |first launched=October 19, 2015 |
− | | first launched | + | |release price=$294 |
− | | | + | |family=Xeon E3 |
− | | | + | |series=E3-1200 v5 |
+ | |locked=Yes | ||
+ | |frequency=2,900 MHz | ||
+ | |turbo frequency1=3,900 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
+ | |clock multiplier=29 | ||
+ | |cpuid=506E3 | ||
+ | |isa=x86-64 | ||
+ | |isa family=x86 | ||
+ | |microarch=Skylake | ||
+ | |platform=Greenlow | ||
+ | |chipset=Sunrise Point | ||
+ | |core name=Skylake DT | ||
+ | |core family=6 | ||
+ | |core model=94 | ||
+ | |core stepping=R0 | ||
+ | |process=14 nm | ||
+ | |technology=CMOS | ||
+ | |die area=122 mm² | ||
+ | |word size=64 bit | ||
+ | |core count=4 | ||
+ | |thread count=8 | ||
+ | |max cpus=1 | ||
+ | |max memory=64 GiB | ||
+ | |v core min=0.55 V | ||
+ | |v core max=1.52 V | ||
+ | |tdp=45 W | ||
+ | |tjunc min=0 °C | ||
+ | |tjunc max=100 °C | ||
+ | |tstorage min=-25 °C | ||
+ | |tstorage max=125 °C | ||
+ | |package module 1={{packages/intel/lga-1151}} | ||
+ | |turbo frequency=Yes | ||
+ | }} | ||
+ | '''Xeon E3-1260L v5''' is an entry-level server and workstation {{arch|64}} [[quad-core]] [[x86]] microprocessor introduced by [[Intel]] in October 2015. This {{intel|Skylake}}-based chip operates at 2.9 GHz with turbo boost of 3.9 GHz. The E3-1260L v5 is a special low-power chip with a TDP of 45 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no [[integrated graphics processor]]. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=256 KiB | ||
+ | |l1i cache=128 KiB | ||
+ | |l1i break=4x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=128 KiB | ||
+ | |l1d break=4x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=1 MiB | ||
+ | |l2 break=4x256 KiB | ||
+ | |l2 desc=4-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=8 MiB | ||
+ | |l3 break=4x2 MiB | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR3L-1600 | ||
+ | |type 2=DDR4-2133 | ||
+ | |ecc=Yes | ||
+ | |max mem=64 GiB | ||
+ | |controllers=1 | ||
+ | |channels=2 | ||
+ | |max bandwidth=31.79 GiB/s | ||
+ | |bandwidth schan=15.89 GiB/s | ||
+ | |bandwidth dchan=31.79 GiB/s | ||
+ | }} | ||
− | + | == Expansions == | |
− | + | {{expansions | |
− | + | | pcie revision = 3.0 | |
− | + | | pcie lanes = 16 | |
− | + | | pcie config = 1x16 | |
− | | | + | | pcie config 2 = 2x8 |
− | + | | pcie config 3 = 1x8+2x4 | |
− | + | }} | |
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− | |||
− | + | == Graphics == | |
− | + | This chip has no integrated graphics processing unit. | |
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− | | | + | == Features == |
− | | | + | {{x86 features |
− | | | + | |real=Yes |
− | | | + | |protected=Yes |
− | | | + | |smm=Yes |
− | | | + | |fpu=Yes |
− | | | + | |x8616=Yes |
− | | | + | |x8632=Yes |
− | | | + | |x8664=Yes |
− | | | + | |nx=Yes |
− | | | + | |mmx=Yes |
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
− | | | + | |abm=Yes |
− | | | + | |tbm=No |
− | | | + | |bmi1=Yes |
− | | | + | |bmi2=Yes |
− | | | + | |fma3=Yes |
− | | | + | |fma4=No |
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=No | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=Yes | ||
+ | |sgx=Yes | ||
+ | |securekey=Yes | ||
+ | |osguard=Yes | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
}} | }} | ||
− |
Latest revision as of 16:26, 13 December 2017
Edit Values | ||||||||||||
Xeon E3-1260L v5 | ||||||||||||
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General Info | ||||||||||||
Designer | Intel | |||||||||||
Manufacturer | Intel | |||||||||||
Model Number | E3-1260L v5 | |||||||||||
Part Number | CM8066201921903 | |||||||||||
S-Spec | SR2CR, SR2LH | |||||||||||
Market | Server | |||||||||||
Introduction | October 19, 2015 (announced) October 19, 2015 (launched) | |||||||||||
Release Price | $294 | |||||||||||
Shop | Amazon | |||||||||||
General Specs | ||||||||||||
Family | Xeon E3 | |||||||||||
Series | E3-1200 v5 | |||||||||||
Locked | Yes | |||||||||||
Frequency | 2,900 MHz | |||||||||||
Turbo Frequency | Yes | |||||||||||
Turbo Frequency | 3,900 MHz (1 core) | |||||||||||
Bus type | DMI 3.0 | |||||||||||
Bus rate | 4 × 8 GT/s | |||||||||||
Clock multiplier | 29 | |||||||||||
CPUID | 506E3 | |||||||||||
Microarchitecture | ||||||||||||
ISA | x86-64 (x86) | |||||||||||
Microarchitecture | Skylake | |||||||||||
Platform | Greenlow | |||||||||||
Chipset | Sunrise Point | |||||||||||
Core Name | Skylake DT | |||||||||||
Core Family | 6 | |||||||||||
Core Model | 94 | |||||||||||
Core Stepping | R0 | |||||||||||
Process | 14 nm | |||||||||||
Technology | CMOS | |||||||||||
Die | 122 mm² | |||||||||||
Word Size | 64 bit | |||||||||||
Cores | 4 | |||||||||||
Threads | 8 | |||||||||||
Max Memory | 64 GiB | |||||||||||
Multiprocessing | ||||||||||||
Max SMP | 1-Way (Uniprocessor) | |||||||||||
Electrical | ||||||||||||
Vcore | 0.55 V-1.52 V | |||||||||||
TDP | 45 W | |||||||||||
Tjunction | 0 °C – 100 °C | |||||||||||
Tstorage | -25 °C – 125 °C | |||||||||||
Packaging | ||||||||||||
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Xeon E3-1260L v5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 2.9 GHz with turbo boost of 3.9 GHz. The E3-1260L v5 is a special low-power chip with a TDP of 45 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no integrated graphics processor.
Cache[edit]
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Graphics[edit]
This chip has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
Facts about "Xeon E3-1260L v5 - Intel"
l1d$ description | 8-way set associative + |
l1i$ description | 8-way set associative + |
l2$ description | 4-way set associative + |