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Difference between revisions of "intel/mobile pentium ii/300pe"
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m (Bot: moving all {{mpu}} to {{chip}})
 
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{{intel title|Mobile Pentium II 300PE}}
 
{{intel title|Mobile Pentium II 300PE}}
{{mpu
+
{{chip
 
| name                = Mobile Pentium II 300PE
 
| name                = Mobile Pentium II 300PE
 
| no image            = Yes
 
| no image            = Yes
Line 10: Line 10:
 
| model number        = 300PE
 
| model number        = 300PE
 
| part number        = PMG30002002AA
 
| part number        = PMG30002002AA
| part number 1       = KP80524KX300256
+
| part number 2       = KP80524KX300256
| part number 2       = KC80524KX300256
+
| part number 3       = KC80524KX300256
 
| market              = Mobile
 
| market              = Mobile
 
| first announced    = 1998
 
| first announced    = 1998
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| thread count        = 1
 
| thread count        = 1
 
| max cpus            = 1
 
| max cpus            = 1
| max memory          = 64 GB
+
| max memory          = 64 GiB
 +
 
  
| electrical          = Yes
 
 
| power              =  
 
| power              =  
 
| v core              = 1.6
 
| v core              = 1.6
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This is an improvement from the original {{intel|Mobile Pentium II}} ({{\\|300}}) chips which had a larger (512 KB) L2$ but operated at half core speed while being manufactured on a separate die and packaged together.
 
This is an improvement from the original {{intel|Mobile Pentium II}} ({{\\|300}}) chips which had a larger (512 KB) L2$ but operated at half core speed while being manufactured on a separate die and packaged together.
 
== Cache ==
 
== Cache ==
{{main|intel/microarchitectures/p6#Memory_Hierarchy|l1=P6's Cache}}
+
{{main|intel/microarchitectures/p6#Memory_Hierarchy|l1=P6 § Cache}}
 
{{cache info
 
{{cache info
|l1i cache=16 KB
+
|l1i cache=16 KiB
|l1i break=1x16 KB
+
|l1i break=1x16 KiB
 
|l1i desc=4-way set associative
 
|l1i desc=4-way set associative
 
|l1i extra=
 
|l1i extra=
|l1d cache=16 KB
+
|l1d cache=16 KiB
|l1d break=1x16 KB
+
|l1d break=1x16 KiB
 
|l1d desc=4-way set associative
 
|l1d desc=4-way set associative
 
|l1d extra=
 
|l1d extra=
|l2 cache=256 KB
+
|l2 cache=256 KiB
|l2 break=1x256 KB
+
|l2 break=1x256 KiB
 
|l2 desc=4-way set associative
 
|l2 desc=4-way set associative
 
|l2 extra=(on-die)
 
|l2 extra=(on-die)
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== Features ==
 
== Features ==
{{mpu features
+
{{x86 features
 
| mmx        = Yes
 
| mmx        = Yes
 
}}
 
}}

Latest revision as of 15:25, 13 December 2017

Edit Values
Mobile Pentium II 300PE
General Info
DesignerIntel
ManufacturerIntel
Model Number300PE
Part NumberPMG30002002AA,
KP80524KX300256,
KC80524KX300256
S-SpecSL3HJ, SL32R, SL32N
MarketMobile
Introduction1998 (announced)
January 25, 1999 (launched)
ShopAmazon
General Specs
FamilyMobile Pentium II
LockedYes
Frequency300 MHz
Bus typeFSB
Bus speed66 MHz
Clock multiplier4.5
CPUID066Ah
Microarchitecture
MicroarchitectureP6
Core NameDixon
Core Family6
Core Model6
Core SteppingmdpA0, mdbA0, mdxA0
Process250 nm
Transistors27,400,000
TechnologyCMOS
Die180 mm²
Word Size32 bit
Cores1
Threads1
Max Memory64 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1.6 ± 0.12 V
TDP11.6 W
OP Temperature-40 °C – 85 °C

The Mobile Pentium II 300PE was a 32-bit x86 microprocessor, part of the second batch ("Performance Enhanced") of the Mobile Pentium II family. This MPU operated at 300 MHz and had a TDP of 11.6 Watts. This chip was manufactured in 250 nm process and includes a smaller 256 KB of L2$ on-die.

This is an improvement from the original Mobile Pentium II (300) chips which had a larger (512 KB) L2$ but operated at half core speed while being manufactured on a separate die and packaged together.

Cache[edit]

Main article: P6 § Cache
Cache Info [Edit Values]
L1I$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 4-way set associative
L1D$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 4-way set associative
L2$ 256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
1x256 KiB 4-way set associative (on-die)

Graphics[edit]

This processor has no integrated graphics processing unit.

Memory controller[edit]

This processor has no integrated memory controller.

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
l1d$ description4-way set associative +
l1i$ description4-way set associative +
l2$ description4-way set associative +