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Difference between revisions of "intel/mobile pentium ii/233"
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{{intel title|Mobile Pentium II 233}} | {{intel title|Mobile Pentium II 233}} | ||
| − | {{ | + | {{chip |
| name = Mobile Pentium II 233 | | name = Mobile Pentium II 233 | ||
| no image = Yes | | no image = Yes | ||
| Line 10: | Line 10: | ||
| model number = 233 | | model number = 233 | ||
| part number = 80523TX233512 | | part number = 80523TX233512 | ||
| − | | part number | + | | part number 2 = PMD23305001AA |
| − | | part number | + | | part number 3 = PMD23305002AB |
| − | | part number | + | | part number 4 = PME23305001AA |
| market = Mobile | | market = Mobile | ||
| first announced = May, 1997 | | first announced = May, 1997 | ||
| Line 51: | Line 51: | ||
| thread count = 1 | | thread count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 64 | + | | max memory = 64 GiB |
| + | |||
| − | |||
| power = | | power = | ||
| v core = 1.6 | | v core = 1.6 | ||
| Line 75: | Line 75: | ||
== Cache == | == Cache == | ||
| − | {{main|intel/microarchitectures/p6#Memory_Hierarchy|l1=P6 | + | {{main|intel/microarchitectures/p6#Memory_Hierarchy|l1=P6 § Cache}} |
{{cache info | {{cache info | ||
| − | |l1i cache=16 | + | |l1i cache=16 KiB |
| − | |l1i break=1x16 | + | |l1i break=1x16 KiB |
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=16 | + | |l1d cache=16 KiB |
| − | |l1d break=1x16 | + | |l1d break=1x16 KiB |
|l1d desc=4-way set associative | |l1d desc=4-way set associative | ||
|l1d extra= | |l1d extra= | ||
| − | |l2 cache=512 | + | |l2 cache=512 KiB |
| − | |l2 break=1x512 | + | |l2 break=1x512 KiB |
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
|l2 extra=(separate die, same package) | |l2 extra=(separate die, same package) | ||
| Line 102: | Line 102: | ||
== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| mmx = Yes | | mmx = Yes | ||
}} | }} | ||
Latest revision as of 15:25, 13 December 2017
| Edit Values | |
| Mobile Pentium II 233 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | 233 |
| Part Number | 80523TX233512, PMD23305001AA, PMD23305002AB, PME23305001AA |
| S-Spec | SL2KH, SL2RQ, SL2U8 |
| Market | Mobile |
| Introduction | May, 1997 (announced) April 2, 1998 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | Mobile Pentium II |
| Locked | Yes |
| Frequency | 233 MHz |
| Bus type | FSB |
| Bus speed | 66 MHz |
| Clock multiplier | 3.5 |
| CPUID | 0650h, 0652h |
| Microarchitecture | |
| Microarchitecture | P6 |
| Core Name | Tonga |
| Core Family | 6 |
| Core Model | 5 |
| Core Stepping | mdA0, mdB0, mdA0 |
| Process | 250 nm |
| Transistors | 7,500,000 |
| Technology | CMOS |
| Die | 131 mm² |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 64 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Vcore | 1.6 ± 0.12 V |
| TDP | 9 W |
| OP Temperature | -40 °C – 85 °C |
The Mobile Pentium II 233 was a 32-bit x86 microprocessor, the first of the Mobile Pentium II family. This processor operated at 233 MHz and had a TDP of 9 Watts. This chip was manufactured in 250 nm process and included a larger 512 KB of L2$ on package, but on a separate die.
Contents
Cache[edit]
- Main article: P6 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative |
| L1D$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative |
| L2$ | 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB |
1x512 KiB 4-way set associative (separate die, same package) |
Graphics[edit]
This processor has no integrated graphics processing unit.
Memory controller[edit]
This processor has no integrated memory controller.
Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Mobile Pentium II 233 - Intel"
| l1d$ description | 4-way set associative + |
| l1i$ description | 4-way set associative + |
| l2$ description | 4-way set associative + |